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Ali Keshavarzi

from Portland, OR
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Also known as:
A Keshavarzi, Ali Keshavarsi, Ali Keshavarvi
Phone and address:
2341 Birkendene St, Portland, OR 97229
(503) 203-1069
Connected to:
Albert Keshavarzi, 63Arash Keshavarz, 39Bhaktha Keshavachar, 57Kiran Keshava, 42Ramesh Keshav, 36Sanjai S Keshavan, 55Shadi Keshavarz, 30Suresh Keshava, 68Alisha Keshavjee, 34Joseph Keshawna, 35

Ali Keshavarzi Phones & Addresses

  • 2341 Birkendene St, Portland, OR 97229 (503) 203-1069
  • 20083 Northcrest Sq, Cupertino, CA 95014
  • 400 San Domingo Way, Los Altos, CA 94022
  • Albuquerque, NM
  • Knox, TN
  • Hillsboro, OR

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Resumes

Resumes

Ali Keshavarzi Photo 1

Vice President Of R And D

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Cypress Semiconductor Corporation
Vice President of R and D
Globalfoundries Jan 2011 - Jul 2012
Fellow and Director of Advanced Technology
Tsmc 2008 - Jan 2011
Director
Intel Corporation 1991 - 2008
Principal Research Scientist
Education:
Purdue University 1986 - 1992
Doctorates, Doctor of Philosophy, Electrical Engineering
Skills:
Microprocessors
Semiconductor Industry
Testing
Power Management
Semiconductors
Analog Circuit Design
Ic
Integrated Circuit Design
Semiconductor Device
Management
Cross Functional Team Leadership
Physical Design
Debugging
Spc
Product Engineering
Spice
Static Timing Analysis
Manufacturing
Architecture
Leadership
Process Engineering
Ali Keshavarzi Photo 2

Research Scientist

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Location:
Portland, OR
Industry:
Semiconductors
Work:
Intel Corporation
Research Scientist
Education:
Purdue University 1985 - 1992

Publications

Us Patents

Employing Transistor Body Bias In Controlling Chip Parameters

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US Patent:
6411156, Jun 25, 2002
Filed:
Dec 30, 1998
Appl. No.:
09/224575
Inventors:
Shekhar Y. Borkar - Beaverton OR
Vivek K. De - Beaverton OR
Ali Keshavarzi - Portland OR
Siva G. Narendra - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 301
US Classification:
327534, 327545
Abstract:
In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control a setting of a body bias signal to control body biases provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal being responsive to an input signal to the control circuitry. In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control settings of a body bias signal, a supply voltage signal, and a clock signal to control body biases, supply voltages, and clock frequencies provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal, supply voltage signal, and clock signal being responsive to an input signal to the control circuitry.

Multiple Parameter Testing With Improved Sensitivity

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US Patent:
6459293, Oct 1, 2002
Filed:
Sep 29, 2000
Appl. No.:
09/672695
Inventors:
Ali Keshavarzi - Portland OR
Kaushik K. Roy - West Lafayette IN
Vivek K. De - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G01R 3126
US Classification:
324765, 324763
Abstract:
A method and device are provided for testing electronic devices on a chip. This may be accomplished by measuring current through a first electronic device and measuring a speed of the first electronic device. A determination may then be made whether the first electronic device is defective by comparing the measured current and the measured speed with a multi-parameter (i. e. , IDDQ and FMAX) threshold level.

Software Control Of Transistor Body Bias In Controlling Chip Parameters

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US Patent:
6484265, Nov 19, 2002
Filed:
Dec 30, 1998
Appl. No.:
09/224573
Inventors:
Shekhar Y. Borkar - Beaverton OR
Vivek K. De - Beaverton OR
Ali Keshavarzi - Portland OR
Siva G. Narendra - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 132
US Classification:
713324, 327544
Abstract:
In some embodiments, the invention includes a system having a processor and control circuitry. The control circuitry controls a setting of a body bias signal to control body biases provided in the processor to at least partially control a parameter of the processor, wherein the control circuitry controls the setting responsive to processor signal resulting for execution of software. The control circuitry may further control settings of a supply voltage signal and a clock signal to control the parameter. More than one parameter may be controlled. Examples of the parameters include performance, power consumption, and temperature.

Dual Threshold Sram Cell For Single-Ended Sensing

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US Patent:
6519176, Feb 11, 2003
Filed:
Sep 29, 2000
Appl. No.:
09/675579
Inventors:
Fatih Hamzaoglu - Beaverton OR
Ali Keshavarzi - Portland OR
Yibin Ye - Hillsboro OR
Siva G. Narendra - Beaverton OR
Vivek K. De - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 1100
US Classification:
365154, 365156, 365203
Abstract:
A six transistor SRAM cell for single-ended sensing is described along with related memory architecture. The cell comprises a bistable circuit connected to complementary bit lines through a pair of passgate transistors. One of the passgate transistors has a lower threshold voltage than the other transistor. The lower threshold voltage is used to couple the cell to a single-ended sense amplifier through one of the bit lines. In one embodiment fewer than all the bit lines in an array are precharged in order to reduce power consumption in the array.

Switched Current Source

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US Patent:
6545619, Apr 8, 2003
Filed:
Dec 28, 2001
Appl. No.:
10/040903
Inventors:
Jaume A. Segura - Palma de Mallorca, ES
Jose L. Rossello - Palma de Mallorca, ES
Ali Keshavarzi - Portland OR
Siva G. Narendra - Portland OR
Vivek K. De - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03M 166
US Classification:
341136, 341150
Abstract:
A circuit includes a switched current source having a switching transistor coupled in series to a bias transistor. An isolation transistor is coupled in series to an output of the switched current source. The width of the switching transistor is greater than the width of the isolation transistor.

Circuit Including Forward Body Bias From Supply Voltage And Ground Nodes

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US Patent:
6593799, Jul 15, 2003
Filed:
Sep 21, 2001
Appl. No.:
09/957996
Inventors:
Vivek K. De - Beaverton OR
Ali Keshavarzi - Portland OR
Siva G. Narendra - Beaverton OR
Shekhar Y. Borkar - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 301
US Classification:
327534, 327537
Abstract:
One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.

Silicon On Insulator Device Design Having Improved Floating Body Effect

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US Patent:
6632686, Oct 14, 2003
Filed:
Sep 29, 2000
Appl. No.:
09/672696
Inventors:
Ali Keshavarzi - Portland OR
Siva G. Narendra - Beaverton OR
James W. Tschanz - Hillsboro OR
Vivek K. De - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2166
US Classification:
438 14, 438 3, 438149
Abstract:
A method is provided for designing an electronic device. This may include determining a capacitance ratio of a design of the electronic device and altering the design so as to increase the capacitance ratio of said electronic device. The capacitance ratio may be C /(C +C +C ), where C is a capacitance of a drain-body junction, C is a capacitance of a source-body junction and C is a capacitance of a buried oxide layer.

Method And Apparatus For Providing Rotational Burn-In Stress Testing

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US Patent:
6683467, Jan 27, 2004
Filed:
Sep 29, 2000
Appl. No.:
09/672689
Inventors:
Ali Keshavarzi - Portland OR
David M. Wu - Austin TX
Yibin Ye - Hillsboro OR
Vivek K. De - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G01R 3102
US Classification:
324760, 3241581
Abstract:
A method and device are provided for stress testing a chip. The chip may be partitioned into at least a first block and a second block. Burn-in stress testing may be performed on electronic devices within the first block without simultaneously performing burn-in stress testing on electronic devices within the second block. A burn-in stress testing device may perform the burn-in testing. A control device may be coupled to the burn-in stress testing device to enable burn-in stress testing on electronic devices within at least the first block of the chip without simultaneously enabling burn-in stress testing on the second block of the chip.

Isbn (Books And Publications)

Microelectronic Manufacturing Yield, Reliability & Failure Analysis III: 1-2 October 1997 Austin, Texas

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Author

Ali Keshavarzi

ISBN #

0819426482

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Ali Keshavarzi from Portland, OR Get Report