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Ali Feiz Zarrin Ghalam

from Sunnyvale, CA
Age ~50
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Also known as:
Ali Zarrin Ghalam, Ali F Ghalam, Ali Feiz, Ali Feizzarrin M, Ali M, I N, Z Zarringhalam
Phone and address:
591 Arran Ct, Sunnyvale, CA 94087
Related to:
Feiz Z GhalamParaston Z Ghalam
Connected to:
Daryoush C Ghalambor, 47Dina F Ghalayini, 67Mohammad O Ghalayini, 75Mustafa S Ghalayini, 31Sarah Ghalayini, 27Souraya Ghalayini, 50Touline T Ghalayini, 49Soraya E Ghalchi, 68Arjun Ghale, 43Khem R Ghale, 40

Ali Ghalam Phones & Addresses

  • 591 Arran Ct, Sunnyvale, CA 94087
  • La Jolla, CA
  • San Jose, CA
  • Los Angeles, CA
  • Cleveland, OH

Resumes

Resumes

Ali Ghalam Photo 1

Director Of Design Engineering

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Location:
591 Arran Ct, Sunnyvale, CA 94087
Industry:
Semiconductors
Work:
Micron Technology
Director of Design Engineering
Education:
University of Southern California 2001 - 2006
Doctorates, Doctor of Philosophy, Electrical Engineering Sharif University of Technology 1992 - 1997
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Semiconductors
Flash Memory
Ic
Asic
Verilog
Cmos
Mixed Signal
Circuit Design
Analog Circuit Design
Integrated Circuit Design
Analog
Vlsi
Simulations
Low Power Design
Soc
Embedded Systems
Languages:
English
Farsi
Ali Ghalam Photo 2

Ali Ghalam

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Publications

Us Patents

Method And Apparatus For Addressing Memory Arrays

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US Patent:
20120230110, Sep 13, 2012
Filed:
Mar 11, 2011
Appl. No.:
13/046248
Inventors:
Dean Nobunaga - Cupertino CA, US
Terry Grunzke - Boise ID, US
Ali Ghalam - San Jose CA, US
International Classification:
G11C 16/04
G11C 7/00
US Classification:
36518518, 365191
Abstract:
The present description relates to non-volatile memory arrays and the operation thereof In at least one embodiment, the non-volatile memory array may include a plurality of memory modules coupled in a daisy chain with enable in/out signals, and a single chip enable signal coupled in parallel to each memory module. With such a configuration, all memory units within each of the memory modules of each memory array may be addressed with the single chip enable

Auto-Suspend And Auto-Resume Operations For A Multi-Die Nand Memory Device

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US Patent:
20140293704, Oct 2, 2014
Filed:
Mar 28, 2013
Appl. No.:
13/852992
Inventors:
Ali Ghalam - San Jose CA, US
Dean Nobunaga - Cupertino CA, US
Jason Guo - San Jose CA, US
International Classification:
G11C 16/30
US Classification:
36518518
Abstract:
A method and apparatus that controls a peak-current condition in a multi-die memory, such as a solid-state drive, by determining by at least one die of the multi-die memory whether a subsequent memory operation is a high-current memory operation, such as an operation to enable a charge pump of the die, an operation to charge a bit line of the die, or a program/erase loop operation, or a combination thereof. The die enters a suspended-operation mode if the subsequent memory operation is determined to be a high current memory operation. Operation is resumed by the die in response to a resume operation event, such as, but not limited to, a command specifically address to the die, an indication from another die that a high-current memory operation is complete. Once operation is resumed, the die performs the high-current memory operation.
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Ali Feiz Zarrin Ghalam from Sunnyvale, CA, age ~50 Get Report