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Ali Reza Farhang

from Beaverton, OR
Age ~57
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Also known as:
Ali R Farhang, Ali Living Farhang, Reza Farhang Ali, Farhang Ali
Phone and address:
16720 Blackberry Ln, Beaverton, OR 97007
(503) 642-0146
Related to:
Marilyn Skinner Lanier, 78Mehri M Alba, 58Safoura Mirfakhrae FarhangFarhang AliAdeleh Jozavi, 66Abolfazl Alba, 94Mohammad Alba, 62Fatemeh F Farhang, 59Haaniyeh Alba, 80
Connected to:
Alireza Farhang, 44Amir M Farhang, 51Eric F Farhang, 35Michelle N Farhang, 33Nina Farhang, 101Ray R Farhang, 75Seyedhamid Farhangi, 60Amel Farhat, 51Andrew J Farhat, 47Chadi S Farhat, 48

Ali Farhang Phones & Addresses

  • 16720 Blackberry Ln, Aloha, OR 97007 (503) 642-0146
  • 7708 Leland Dr, Beaverton, OR 97007
  • 6123 SW Sheridan St, Portland, OR 97225 (503) 703-0026
  • Austin, TX
  • Sandy, UT

Work

Position: Food Preparation and Serving Related Occupations

Education

Degree: Associate degree or higher

Resumes

Resumes

Ali Farhang Photo 1

Member Of The Board Of Advisors

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Location:
Portland, OR
Industry:
Semiconductors
Work:
Alphawave
Member of the Board of Advisors
Intel Corporation 2009 - 2017
Vice President of Engineering: Ipsg General Manager of Technology Platform Enablement Group
Intel Corporation 2006 - 2009
Director of Engineering : Logic Technology Development Group
Intel Corporation 2001 - 2006
Product Manager, Director of Engineering : Ltd Microprocessor Development Group
Intel Corporation 1996 - 2001
Microprocessor Design Manager
Education:
Stanford University Graduate School of Business 2014 - 2014
University of Utah 1989 - 1991
Masters, Electrical Engineering Oklahoma State University 1985 - 1989
Bachelors, Electrical Engineering University of Isfahan
Bachelors
Skills:
Semiconductors
Ic
Asic
Soc
Product Management
Embedded Systems
Eda
Vlsi
Cross Functional Team Leadership
Verilog
Debugging
Cmos
Processors
Integrated Circuits
Application Specific Integrated Circuits
Perl
Analog Circuit Design
System on A Chip
Timing Closure
Very Large Scale Integration
Microprocessors
Integrated Circuit Design
Semiconductor Industry
Project Management
Organizational Leadership
Strategic Leadership
Acquisitions
Engineering Management
Cross Functional Collaborations
Program Management
Computer Architecture
Ali Farhang Photo 2

Technician

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Industry:
Construction
Work:
Tech Sulotions
Technician
Omran Holding Group
Site Engineer
Ali Farhang Photo 3

Ali Farhang

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Location:
Portland, OR
Ali Farhang Photo 4

Ali Farhang

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Publications

Us Patents

Programmable Weak Write Test Mode

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US Patent:
6778450, Aug 17, 2004
Filed:
May 8, 2002
Appl. No.:
10/141805
Inventors:
Eric B. Selvin - San Jose CA
Ali R. Farhang - Beaverton OR
Douglas A. Guddat - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 700
US Classification:
365201, 365154, 36518522, 36518909, 365190, 36523006
Abstract:
A new programmable weak write circuit is defined with the ability to perform SRAM weak write testing at multiple stress strength settings which track process variation. Prior art weak write test circuitry is designed to test a population of SRAM devices at a fixed weak write stress strength as determined by the best available pre-silicon design environmental factors. This design may over- or under-test SRAM cells for the target defects due to poor process tracking characteristics and may require multiple post-silicon design iterations to keep up with environmental changes following initial design. In the new circuit, multiple settings are designed in pre-silicon to account for the expected uncertainty in environmental factors. During post-silicon testing, a suitable stress setting is selected based on an acceptable or predetermined quality versus test yield tradeoff and its suitability is re-evaluated following any significant environmental changes to determine if a different stress setting is necessary.

Sram With Forward Body Biasing To Improve Read Cell Stability

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US Patent:
6985380, Jan 10, 2006
Filed:
Mar 26, 2004
Appl. No.:
10/810093
Inventors:
Muhammad M. Khellah - Lake Oswego OR, US
Dinesh Somasekhar - HIllsboro OR, US
Yibin Ye - Hillsboro OR, US
Ali R. Farhang - Beaverton OR, US
Gunjan H. Pandya - Beaverton OR, US
Vivek K. De - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 11/412
US Classification:
365156, 365154, 365226, 36518909
Abstract:
A SRAM memory cell comprising cross-coupled inverters, each cross-coupled inverter comprising a pull-up transistor, where the pull-up transistors are forward body biased during read operations. Forward body biasing improves the read stability of the memory cell. Other embodiments are described and claimed.

Buffer Circuit Having Variable Output Impedance

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US Patent:
56062753, Feb 25, 1997
Filed:
Sep 5, 1995
Appl. No.:
8/523165
Inventors:
Ali R. Farhang - Beaverton OR
Scott G. Nogle - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H03K 19084
US Classification:
327108
Abstract:
An output buffer circuit (20) has an output impedance that is adjustable. An external resistor (32) having a resistance that is a multiple of the desired output impedance is coupled to the output buffer circuit (20). A voltage across the resistor (32) is converted to a digital code using an analog-to-digital (A/D) converter (22). A digital code from the A/D converter (24) is used to adjust a resistance of a binary weighed transistor array (45) to match the resistance of the external resistor (32). A plurality of binary weighted output transistors (153, 154, 155) are selected in response to the digital code to adjust the output impedance to match the characteristic impedance of a load driven by the output buffer circuit (20). The output impedance is easily adjustable by changing the resistance of external resistor (32), allowing the output buffer circuit to drive various load impedances.
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Ali Reza Farhang from Beaverton, OR, age ~57 Get Report