Resumes
Resumes
Ali Adl-Tabatabai Phones & Addresses
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San Jose, CA
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2125 Quinn Ave, Santa Clara, CA 95051
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Pittsburgh, PA
Publications
Us Patents
Methods And Systems For Transactional Nested Parallelism
View pageUS Patent:
20100162247, Jun 24, 2010
Filed:
Dec 19, 2008
Appl. No.:
12/340374
Inventors:
Adam Welc - San Francisco CA, US
Haris Volos - Madison WI, US
Ali Adl-Tabatabai - San Jose CA, US
Tatiana Shpeisman - Menlo Park CA, US
Haris Volos - Madison WI, US
Ali Adl-Tabatabai - San Jose CA, US
Tatiana Shpeisman - Menlo Park CA, US
International Classification:
G06F 9/46
US Classification:
718101
Abstract:
Methods and systems for executing nested concurrent threads of a transaction are presented. In one embodiment, in response to executing a parent transaction, a first group of one or more concurrent threads including a first thread is created. The first thread is associated with a transactional descriptor comprising a pointer to the parent transaction.
Efficient And Consistent Software Transactional Memory
View pageUS Patent:
20120016853, Jan 19, 2012
Filed:
Sep 27, 2011
Appl. No.:
13/246678
Inventors:
Cheng Wang - San Ramon CA, US
Youfeng Wu - Palo Alto CA, US
Wei-Yu Chen - Santa Clara CA, US
Bratin Saha - Santa Clara CA, US
Ali Reza Adl-Tabatabai - San Jose CA, US
Youfeng Wu - Palo Alto CA, US
Wei-Yu Chen - Santa Clara CA, US
Bratin Saha - Santa Clara CA, US
Ali Reza Adl-Tabatabai - San Jose CA, US
International Classification:
G06F 7/00
US Classification:
707703, 707E17005
Abstract:
A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In addition, a global timestamp (GTS) is utilized to track a latest committed transaction. Each transaction is associated with a local timestamp (LTS) initialized to the GTS value at the start of a transaction. As a transaction commits it updates the GTS to a new value and sets versions of modified locations to the new value. Pending transactions compare versions determined in read barriers to their LTS. If the version is greater than their LTS indicating another transaction has committed after the pending transaction started and initialized the LTS, then the pending transaction validates its read set to maintain efficient and consistent transactional execution.
Hierarchical Software Path Profiling
View pageUS Patent:
6848100, Jan 25, 2005
Filed:
Mar 31, 2000
Appl. No.:
09/541399
Inventors:
Youfeng Wu - Palo Alto CA, US
Ali Adl-Tabatabai - Santa Clara CA, US
David A. Berson - Marietta GA, US
Jesse Fang - San Jose CA, US
Rajiv Gupta - Tucson AZ, US
Ali Adl-Tabatabai - Santa Clara CA, US
David A. Berson - Marietta GA, US
Jesse Fang - San Jose CA, US
Rajiv Gupta - Tucson AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 945
US Classification:
717157, 717133
Abstract:
A hierarchical software profiling mechanism that gathers hierarchical path profile information has been described. Software to be profiled is instrumented with instructions that save an outer path sum when an inner region is entered, and restore the outer path sum when the inner region is exited. When the inner region is being executed, an inner path sum is generated and a profile indicator representing the inner path traversed is updated prior to the outer path sum being restored. The software to be profiled is instrumented using information from augmented control flow graphs that represent the software.