Search

Alfred Francis Lauriello

from Plano, TX
Age ~78
Get Report
Also known as:
Alfred F Lauriello, Fred Lauriello, Af Lauriello, Alfredo Lauriello, Lauriello Af
Phone and address:
1612 Sylvan Dr, Plano, TX 75074
Related to:
Fred Lauriello
Connected to:
Carolyn Laurienti, 41Jesse A Laurienti, 35Mia D Laurienzo, 53Mollie J Laurienzo, 44Rocco Laurienzo, 58Daniel Laurila, 63Inga J Laurila, 74Linda K Laurila, 68Kevin M Laurilla, 52Ahern C Laurinat, 41

Alfred Lauriello Phones & Addresses

  • 1612 Sylvan Dr, Plano, TX 75074

Publications

Us Patents

Multipin Coupler

View page
US Patent:
43879462, Jun 14, 1983
Filed:
Dec 24, 1980
Appl. No.:
6/273843
Inventors:
Alfred F. Lauriello - Plano TX
Steven D. Swendrowski - The Colony TX
Assignee:
Mostek Corporation - Carrollton TX
International Classification:
H01R 13631
H01R 13631
US Classification:
339 66M
Abstract:
A multipin coupler (50) includes upper and lower ring members (52, 54) with a plurality of cooperating pin connections (76) surrounding central openings therethrough such that the circuitry and corresponding probe card for testing an IC chip can be interconnected through leads of the same lengths having uniform impedances. Guide pins (68) are provided to assure proper alignment of the ring members (52, 54) before engagement of the pin connections (76). A pin and slot connection supports the upper ring member (52) for limited movement relative to the lower ring member (54) for adjustability.

Test Apparatus For Circuits Having A Multiplex Input/Output Terminal Including A Load Connected To The Terminal Together With Circuitry For Monitoring The Current Flow Through The Load When Inputting A Signal To The Terminal

View page
US Patent:
44726783, Sep 18, 1984
Filed:
Aug 10, 1981
Appl. No.:
6/292918
Inventors:
Alfred F. Lauriello - Plano TX
Assignee:
Mostek Corporation - Carrollton TX
International Classification:
G01R 1512
G01R 3128
US Classification:
324 73R
Abstract:
A test circuit (10) provides high and low reference voltages to a circuit (92) under test. A load (52) is connected to a multiplexed terminal (90) of circuit (92). A current source transistor (48) and a current sink transistor (132) are connected to provide current through load (52). A feedback network is connected to the current source transistor (48) and a second feedback network is connected to the current sink transistor (132). The feedback signals are compared to the reference voltages to generate control signals for driving the multiplexed terminal (90) accurately to the desired reference voltage. When the circuit (92) under test generates logic signals the load (52) sources or sinks the appropriate current depending upon the voltage states generated by the circuit (92). The voltage states generated at the multiplexed terminal (90) are transmitted through a buffer (148) to an output terminal (156). Thus, the load (52) is connected to the multiplexed terminal (90) at all times to provide the correct load for circuit (92) but does not degrade the reference voltages applied to terminal (90) due to the operation of the feedback networks.
Control profile
Alfred Francis Lauriello from Plano, TX, age ~78 Get Report