Alexei V Bourd

7737985, Jun 15, 2010

Jan 8, 2007

11/621052

William Torzewski - San Diego CA, US
Chun Yu - San Diego CA, US
Alexei V. Bourd - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

G09G 5/36
G06T 15/30
G06T 17/20

345557, 345423

Apparatus are provided including device memory, hardware entities, a sub-image cell value cache, and a cache write operator. At least some of the hardware entities perform actions involving access to and use of the device memory. The hardware entities include 3D graphics circuitry to process, for ready display, 3D images from primitive objects. The cache is separate from the device memory, and is provided to hold data, including buffered sub-image cell values. The cache is connected to the 3D graphics circuitry so that pixel processing portions of the 3D graphics circuitry access the buffered sub-image cell values in the cache, in lieu of the pixel processing portions directly accessing the sub-image cell values in the device memory. The write operator writes the buffered sub-image cell values to the device memory under direction of a priority scheme. The priority scheme preserves in the cache border cell values bordering one or more primitive objects.

7944442, May 17, 2011

Dec 12, 2006

11/609762

Angus M. Dorbie - San Diego CA, US
Alexei V. Bourd - San Diego CA, US
Chun Yu - San Diego CA, US

Qualcomm Incorporated - San Diego CA

G06T 15/40

345421, 345611, 345613, 345614, 345622, 345626

The system includes a shape buffer manager configured to store coverage data in the shape buffer. The coverage data indicates whether each mask pixel is a covered pixel or an uncovered pixel. A mask pixel is a covered pixel when a shape to be rendered on a screen covers the mask pixel such that one or more coverage criteria is satisfied and is an uncovered pixel when the shape does not cover the mask pixel such that the one or more coverage criteria are satisfied. A bounds primitive rasterizer is configured to rasterize a bounds primitive that bounds the shape. The bounds primitive is rasterized into primitive pixels that each corresponds to one of the mask pixels. A pixel screener is configured to employ the coverage data from the shape buffer to screen the primitive pixels into retained pixels and discarded pixels. The retained pixels each corresponds to a mask pixel that the coverage data indicates is a covered pixel and the discarded pixels each correspond to a mask pixels that the coverage data indicates is an uncovered pixel. The system also includes an attribute generator configured to generate pixel attributes for the retained primitive pixels and also configured not to generate pixel attributes for the discarded primitive pixels.

8269775, Sep 18, 2012

Dec 9, 2008

12/331273

Alexei V. Bourd - San Diego CA, US
Guofang Jiao - San Diego CA, US
Jay C. Yun - Carlsbad CA, US

QUALCOMM Incorporated - San Diego CA

G06T 11/20

345442

This disclosure describes techniques for removing vertex points during two-dimensional (2D) graphics rendering using three-dimensional (3D) graphics hardware. In accordance with the described techniques one or more vertex points may be removed during 2D graphics rendering using 3D graphics hardware. For example, the techniques may remove redundant vertex points in the display coordinate space by discarding vertex points that have the substantially same positional coordinates in the display coordinate space as a previous vertex point. Alternatively or additionally, the techniques may remove excess vertex points that lie in a straight line. Removing the redundant vertex points or vertex points that lie in a straight line allow for more efficient utilization of the hardware resources of the GPU and increase the speed at which the GPU renders the image for display.

8355028, Jan 15, 2013

Jul 30, 2007

11/830667

Guofang Jiao - San Diego CA, US
Alexei V. Bourd - San Diego CA, US
Chun Yu - San Diego CA, US
Lingjun Chen - San Diego CA, US
Yun Du - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

G06T 1/00

345522, 345559

A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dimensional (MD) vector register. The hardware packing consecutively packs M components of the shader variables (varyings or attributes) and any remaining variables into a vertex cache or other storage medium.

20060044317, Mar 2, 2006

Aug 30, 2004

10/930408

Alexei Bourd - San Diego CA, US
Shuaib Arshad - San Diego CA, US

G09G 5/36

345557000

A cache stores data for use in rasterizing graphics data. The size of the cache is equal to a selected tile size. A processor performs the rasterization of the graphics image by subdividing the graphics image into a plurality of sub-blocks. The sub-blocks are processed, based on a block processing order, by further subdivision of the sub-blocks into tiles for those sub-blocks that have graphics image data. The tiles have a size equal to the selected tile size. Data, associated with a tile, is loaded into the cache, and the cache data is utilized to generate pixels for the associated tile of the graphics image.

20070273698, Nov 29, 2007

May 25, 2006

11/441696

Yun Du - San Diego CA, US
Guofang Jiao - San Diego CA, US
Chun Yu - San Diego CA, US
Alexei V. Bourd - San Diego CA, US

G06T 1/00

345501

A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.

20090027407, Jan 29, 2009

Jul 24, 2007

11/782509

Alexei V. Bourd - San Diego CA, US
Guofang Jiao - San Diego CA, US
Lin Chen - San Diego CA, US

G06T 1/00

345522

Methods and apparatuses for accessing data within programmable graphics hardware are provided. According to one aspect, a user inserts special log commands into a software program, which is compiled into instructions for the programmable graphics hardware to execute. The hardware writes data to an external memory during runtime according to a flow control protocol, and the software driver reads the data from the memory to display to the user.

20120017069, Jan 19, 2012

Jul 16, 2010

12/837600

Alexei V. Bourd - San Diego CA, US
Guofang Jiao - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

G06F 9/30

712216, 712E09032

Techniques are described for reordering commands to improve the speed at which at least one command stream may execute. Prior to distributing commands in the at least one command stream to multiple pipelines, a multimedia processor analyzes any inter-pipeline dependencies and determines the current execution state of the pipelines. The processor may, based on this information, reorder the at least one command stream by prioritizing commands that lack any current dependencies and therefore may be executed immediately by the appropriate pipeline. Such out of order execution of commands in the at least one command stream may increase the throughput of the multimedia processor by increasing the rate at which the command stream is executed.