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Alexander M Lyashevsky

from Cupertino, CA
Age ~70
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Also known as:
Alexander Lyashevskaya, Alex M Lyashevsky, Lyashevsky Alexander
Phone and address:
11607 Cedar Spring Ct, Cupertino, CA 95014
(408) 865-1594
Related to:
Ilya A Lyashevsky, 44Maria R Lyashevsky, 69Clara R Lyashevsky, 33
Connected to:
Mark Z Lyasko, 57Svetlana M Lyasko, 61Amy Lybarger, 54Andrew J Lybarger, 55Cyle Lybarger, 44Lee H Lybarger, 90Mary Lybarger, 70Melissa A Lybarger, 52Pam Lybarger, 77Patricia A Lybarger, 76

Alexander Lyashevsky Phones & Addresses

  • 11607 Cedar Spring Ct, Cupertino, CA 95014 (408) 865-1594
  • Morgan Hill, CA
  • 11607 Cedar Spring Ct, Cupertino, CA 95014 (408) 398-8560

Work

Company: Intel corporation Jun 2018 Position: Senior director

Education

Degree: Master of Science, Masters School / High School: State University of Management (Sum)

Skills

Gpu • Algorithms • Gpgpu • Opencl • Debugging • Parallel Computing • Microprocessors • Multithreading • Processors • Software Engineering • Computer Architecture • C++ • C • Simulations • Device Drivers • High Performance Computing • H.264 • X86 • Parallel Algorithms • Compilers • Computer Graphics • Opengl • Software Development • Linux • Soc • Video • Image Processing • Parallel Programming • Arm • Scientific Computing • Perl • Optimization • Embedded Software • Software Design • Embedded Systems • Machine Learning • Openmp • Mpi • Digital Signal Processors • Object Oriented Design • Hardware Architecture • Win32 Api • Win32 • Assembly • Video Processing

Emails

a***[email protected]

Industries

Computer Software

Resumes

Resumes

Alexander Lyashevsky Photo 1

Senior Director

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Location:
11607 Cedar Spring Ct, Cupertino, CA 95014
Industry:
Computer Software
Work:
Intel Corporation
Senior Director
Amd Jun 2017 - Jun 2018
Fellow
Amd Jun 2014 - Jun 2017
Pmts, Perceptive Computing Architecture, Radeon Technology Group
Amd Oct 2012 - Jun 2014
Pmts, Amd Research
Amd Oct 2009 - Oct 2012
Pmts, Performance Application Engineering
Education:
State University of Management (Sum)
Master of Science, Masters
Skills:
Gpu
Algorithms
Gpgpu
Opencl
Debugging
Parallel Computing
Microprocessors
Multithreading
Processors
Software Engineering
Computer Architecture
C++
C
Simulations
Device Drivers
High Performance Computing
H.264
X86
Parallel Algorithms
Compilers
Computer Graphics
Opengl
Software Development
Linux
Soc
Video
Image Processing
Parallel Programming
Arm
Scientific Computing
Perl
Optimization
Embedded Software
Software Design
Embedded Systems
Machine Learning
Openmp
Mpi
Digital Signal Processors
Object Oriented Design
Hardware Architecture
Win32 Api
Win32
Assembly
Video Processing

Publications

Us Patents

Resolution Enhancement Of Video Stream Based On Spatial And Temporal Correlation

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US Patent:
8487929, Jul 16, 2013
Filed:
May 3, 2010
Appl. No.:
12/772591
Inventors:
Alexander Lyashevsky - Cupertino CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06T 17/00
US Classification:
345428, 345421, 345441, 345582, 345589, 382167, 382169, 382254
Abstract:
A method and computer program product are provided for resolution enhancement of a video stream based on spatial and temporal correlation. For instance, the method can include predicting interpolated pixels for an image frame of the video stream based on a spatial correlation of pixels in the image frame. The method can also include generating one or more motion vectors for the image frame. Based on the spatially-correlated pixels and the one or more motion vectors, an enhanced image can be reconstructed. Further, the method can include providing a correction factor to one or more pixels in the enhanced image frame.

Decoding Method And System For Highly Compressed Video Data

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US Patent:
20080056348, Mar 6, 2008
Filed:
Aug 31, 2006
Appl. No.:
11/514780
Inventors:
Alexander Lyashevsky - Cupertino CA, US
Jason Yang - San Francisco CA, US
Arcot J. Preetham - Sunnyvale CA, US
International Classification:
H04B 1/66
H04N 11/02
US Classification:
3752401, 37524025
Abstract:
Embodiments of a method and system for decoding video data are described herein. In various embodiments, a high-compression-ratio codec (such as H.264) is part of the encoding scheme for the video data. Embodiments pre-process control maps that were generated from encoded video data, and generating intermediate control maps comprising information regarding decoding the video data. The control maps include information regarding rearranging the video data to be processed in parallel on multiple pipelines of a graphics processing unit (GPU) so as to optimize the use of the multiple pipelines. In an embodiment, decoding is performed on a frame basis such that each of multiple, distinct decoding operations is performed on an entire frame at one time. In other embodiments, processing of different frames is interleaved. Embodiments increase the efficiency of the decoding such as to allow decoding of high-compression-ratio encoded video data on personal computers or comparable equipment without special, additional decoding hardware.

Method And System For Motion Compensation Method In Decoding Of Video Data

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US Patent:
20080056349, Mar 6, 2008
Filed:
Aug 31, 2006
Appl. No.:
11/514801
Inventors:
Alexander Lyashevsky - Cupertino CA, US
Jason Yang - San Francisco CA, US
Arcot J. Preetham - Sunnyvale CA, US
International Classification:
H04B 1/66
H04N 7/12
US Classification:
3752401, 37524012
Abstract:
Embodiments of a method and system for motion compensation in decoding video data are described herein. In various embodiments, a high-compression-ratio codec (such as H.264) is part of the encoding scheme for the video data. Embodiments pre-process control maps that were generated from encoded video data, and generating intermediate control maps comprising information regarding decoding the video data. The control maps indicate which one of multiple prediction operations is to be used in performing motion compensation on particular units of data in a frame. In an embodiment, motion compensation is performed on a frame basis such that each of the multiple prediction operations is performed on an entire frame at one time. In other embodiments, processing of different frames is interleaved. Embodiments increase the efficiency of the motion compensation such as to allow decoding of high-compression-ratio encoded video data on personal computers or comparable equipment without special, additional decoding hardware.

Method And System For Deblocking In Decoding Of Video Data

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US Patent:
20080056350, Mar 6, 2008
Filed:
Aug 31, 2006
Appl. No.:
11/515311
Inventors:
Alexander Lyashevsky - Cupertino CA, US
Jason Yang - San Francisco CA, US
Arcot J. Preetham - Sunnyvale CA, US
International Classification:
H04B 1/66
H04N 11/04
H04N 11/02
US Classification:
3752401, 37524024, 37524025
Abstract:
Embodiments of a method and system for decoding video data are described herein. In various embodiments, a high-compression-ratio codec (such as H.264) is part of the encoding scheme for the video data. Embodiments pre-process control maps that were generated from encoded video data, and generating intermediate control maps comprising information regarding decoding the video data. The control maps include information regarding rearranging the video data to be processed in parallel on multiple pipelines of a graphics processing unit (GPU) so as to optimize the use of the multiple pipelines. In an embodiment, macro blocks of video data with similar deblocking dependencies are identified to be processed together. Deblocking is performed on a frame basis such that deblocking is performed on an entire frame at one time. In other embodiments, processing of different frames is interleaved. Embodiments increase the efficiency of the decoding such as to allow decoding of high-compression-ratio encoded video data on personal computers or comparable equipment without special, additional decoding hardware.

Method And System For Intra-Prediction In Decoding Of Video Data

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US Patent:
20080056363, Mar 6, 2008
Filed:
Aug 31, 2006
Appl. No.:
11/515472
Inventors:
Alexander Lyashevsky - Cupertino CA, US
Jason Yang - San Francisco CA, US
Arcot J. Preetham - Sunnyvale CA, US
International Classification:
H04N 11/04
H04N 11/02
US Classification:
37524013, 37524025
Abstract:
Embodiments of a method and system for intra-prediction in decoding video data are described herein. In various embodiments, a high-compression-ratio codec (such as H.264) is part of the encoding scheme for the video data. Embodiments pre-process control maps that were generated from encoded video data, and generating intermediate control maps comprising information regarding decoding the video data. The control maps indicate which units of video data in a frame are to be processed using an intra-prediction operation. In an embodiment, intra-prediction is performed on a frame basis such that intra-prediction is performed on an entire frame at one time. In other embodiments, processing of different frames is interleaved. Embodiments increase the efficiency of the intra-prediction such as to allow decoding of high-compression-ratio encoded video data on personal computers or comparable equipment without special, additional decoding hardware.

Method And System For Inter-Prediction In Decoding Of Video Data

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US Patent:
20080056364, Mar 6, 2008
Filed:
Aug 31, 2006
Appl. No.:
11/515473
Inventors:
Alexander Lyashevsky - Cupertino CA, US
Jason Yang - San Francisco CA, US
Arcot J. Preetham - Sunnyvale CA, US
International Classification:
H04N 11/04
H04N 11/02
US Classification:
37524013, 37524025
Abstract:
Embodiments of a method and system for inter-prediction in decoding video data are described herein. In various embodiments, a high-compression-ratio codec (such as H.264) is part of the encoding scheme for the video data. Embodiments pre-process control maps that were generated from encoded video data, and generating intermediate control maps comprising information regarding decoding the video data. The control maps indicate which units of video data in a frame are to be processed using an inter-prediction operation. In an embodiment, inter-prediction is performed on a frame basis such that inter-prediction is performed on an entire frame at one time. In other embodiments, processing of different frames is interleaved. Embodiments increase the efficiency of the inter-prediction such as to allow decoding of high-compression-ratio encoded video data on personal computers or comparable equipment without special, additional decoding hardware.

Hierarchical Lossless Compression

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US Patent:
20100299454, Nov 25, 2010
Filed:
May 19, 2009
Appl. No.:
12/468757
Inventors:
Alexander M. Lyashevsky - Cupertino CA, US
Assignee:
ADVANCED MICRO DEVICES, INC. - Sunnyvale CA
International Classification:
G06F 15/16
US Classification:
709247
Abstract:
A method is provided for data compression. The data compression method transforms a square of data into a tile of data. The tile of data is then divided into quads of data that are converted into a representative element, a first delta element, a second delta element, a third delta element, and a control word. A new tile of data is then formed with the representative elements, and the process is repeated until a single representative element remains. The single representative element is then embedded into an output stream with the control words and corresponding delta elements. Decompression of the data is symmetrical to the encoding once the bit stream has been parsed.

Data Driven Micro-Scheduling Of The Individual Processing Elements Of A Wide Vector Simd Processing Unit

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US Patent:
20120151145, Jun 14, 2012
Filed:
Dec 13, 2010
Appl. No.:
12/966808
Inventors:
Alexander M. LYASHEVSKY - Cupertino CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 15/80
G06F 9/02
G06F 12/08
US Classification:
711125, 712 22, 711E12017, 712E09002
Abstract:
A method for optimizing processing in a SIMD core. The method comprises processing units of data within a working domain, wherein the processing includes one or more working items executing in parallel within a persistent thread. The method further comprises retrieving a unit of data from within a working domain, processing the unit of data, retrieving other units of data when processing of the unit of data has finished, processing the other units of data, and terminating the execution of the working items when processing of the working domain has finished.
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Alexander M Lyashevsky from Cupertino, CA, age ~70 Get Report