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Alberto Salleo

from San Francisco, CA
Age ~53
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Related to:
Michele M Salleo, 57Jacqueline L Turnure, 59
Connected to:
Brian J Saller, 53Glen A Saller, 62Grant A Saller, 40Joan A Saller, 71Joshua Saller, 65Lydia S Saller, 76Marjorie D Saller, 100Philip A Saller, 94Tiffany E Saller, 54Cindy Salles, 58

Alberto Salleo Phones & Addresses

  • San Francisco, CA
  • Berkeley, CA
  • Pinole, CA
  • 277 Diamond St, San Francisco, CA 94114

Work

Company: Stanford university Jul 2019 Position: Chair, department of materials science and engineering

Education

School / High School: University of California, Berkeley

Industries

Nanotechnology

Resumes

Resumes

Alberto Salleo Photo 1

Chair, Department Of Materials Science And Engineering

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Location:
San Francisco, CA
Industry:
Nanotechnology
Work:
Stanford University
Chair, Department of Materials Science and Engineering
Stanford University
Professor
Stanford University 2013 - Feb 2019
Associate Professor
Stanford University 2005 - 2012
Assistant Professor
Parc 2001 - 2005
Post-Doc and Member of Research Staff
Education:
University of California, Berkeley
Master In Data Intelligence E Strategie Decisionali - La Sapienza
École Polytechnique

Publications

Us Patents

Method For Fabricating Fine Features By Jet-Printing And Surface Treatment

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US Patent:
6972261, Dec 6, 2005
Filed:
Jun 27, 2002
Appl. No.:
10/186092
Inventors:
William S. Wong - San Carlos CA, US
Steven E. Ready - Santa Cruz CA, US
Stephen D. White - Santa Clara CA, US
Alberto Salleo - San Francisco CA, US
Assignee:
Xerox Corporation - Stamford CT
International Classification:
H01L021/302
US Classification:
438706, 438719, 438763
Abstract:
A method and system for masking a surface to be etched is described. The method includes the operation of heating a phase-change masking material and using a droplet source to eject droplets of a masking material for deposit on a thin-film or other substrate surface to be etched. The temperature of the thin-film or substrate surface is controlled such that the droplets rapidly freeze after upon contact with the thin-film or substrate surface. The thin-film or substrate is then treated to alter the surface characteristics, typically by depositing a self assembled monolayer on the surface. After deposition, the masking material is removed. A material of interest is then deposited over the substrate such that the material adheres only to regions not originally covered by the mask such that the mask acts as a negative resist. Using such techniques, feature sizes of devices smaller than the smallest droplet printed may be fabricated.

Method For Large-Area Patterning Dissolved Polymers By Making Use Of An Active Stamp

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US Patent:
7114448, Oct 3, 2006
Filed:
Nov 6, 2003
Appl. No.:
10/703049
Inventors:
Alberto Salleo - San Francisco CA, US
William S. Wong - San Carlos CA, US
Assignee:
Palo Alto Research Center, Incorporated - Palo Alto CA
International Classification:
C23F 1/00
US Classification:
101493
Abstract:
A method of patterning soluble materials on a substrate is described. In the method, a stamp is applied to a liquid carrier solution. The raised areas of the stamp removes mainly a liquid carrier leaving behind a precipitate while the non-raised areas of the stamp lifts both the liquid carrier and the precipitate from the substrate. The result is a precipitate pattern residue that matches the raised area of the stamp. One use of the method is for patterning large areas of polymers used in large area electronics such as displays and sensors.

Large Area Electronic Device With High And Low Resolution Patterned Film Features

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US Patent:
7125495, Oct 24, 2006
Filed:
Dec 20, 2004
Appl. No.:
11/019037
Inventors:
Robert A. Street - Palo Alto CA, US
William S. Wong - San Carlos CA, US
Alberto Salleo - San Francisco CA, US
Michael L. Chabinyc - Burlingame CA, US
Assignee:
Palo Alto Research Center, Inc. - Palo Alto CA
International Classification:
G01D 15/00
US Classification:
216 27, 438745, 430311
Abstract:
Two different processing techniques are utilized to respectively form high resolution features and low resolution features in a critical layer of an electronic device, and in particular a large area electronic device. High resolution features are formed by soft lithography, and low resolution features are formed by jet-printing or using a jet-printed etch mask. Jet-printing is also used to stitch misaligned structures. Alignment marks are generated with the features to coordinate the various processing steps and to automatically control the stitching process. Thin-film transistors are formed by generating gate structures using a first jet-printed etch mask, forming source/drain electrodes using soft lithography, forming interconnect structures using a second jet-printed etch mask, and then depositing semiconductor material over the source/drain electrodes. Redundant structures are formed to further improve tolerance to misalignment, with non-optimally positioned structures removed (etched) during formation of the low resolution interconnect structures.

Method For Fabricating Fine Features By Jet-Printing And Surface Treatment

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US Patent:
7223700, May 29, 2007
Filed:
Oct 14, 2005
Appl. No.:
11/251525
Inventors:
William S. Wong - San Carlos CA, US
Steven E. Ready - Santa Cruz CA, US
Stephen D. White - Santa Clara CA, US
Alberto Salleo - San Francisco CA, US
Michael L. Chabinyc - Mountain View CA, US
Assignee:
Palo Alto Research Center Incorporated - Palo Alto CA
International Classification:
H01L 21/302
US Classification:
438706, 438725, 438758, 438761
Abstract:
A method and system for masking a surface to be etched is described. The method includes the operation of heating a phase-change masking material and using a droplet source to eject droplets of a masking material for deposit on a thin-film or other substrate surface to be etched. The temperature of the thin-film or substrate surface is controlled such that the droplets rapidly freeze after upon contact with the thin-film or substrate surface. The thin-film or substrate is then treated to alter the surface characteristics, typically by depositing a self assembled monolayer on the surface. After deposition, the masking material is removed. A material of interest is then deposited over the substrate such that the material adheres only to regions not originally covered by the mask such that the mask acts as a negative resist. Using such techniques, feature sizes of devices smaller than the smallest droplet printed may be fabricated.

Thin-Film Transistor Array With Ring Geometry

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US Patent:
7358530, Apr 15, 2008
Filed:
Dec 12, 2003
Appl. No.:
10/734429
Inventors:
William S. Wong - San Carlos CA, US
Jeng Ping Lu - Mountain View CA, US
Alberto Salleo - San Francisco CA, US
Michael L. Chabinyc - Mountain View CA, US
Raj B. Apte - Palo Alto CA, US
Robert A. Street - Palo Alto CA, US
Assignee:
Palo Alto Research Center Incorporated - Palo Alto CA
International Classification:
H01L 29/04
US Classification:
257 59, 257 72, 257E27131
Abstract:
An improved transistor array for a display or sensor device is described. The display or sensor device includes a plurality of pixels. Each pixel includes a width and a length. Each pixel is addressed by a transistor. The transistor addressing each pixel has a channel with a channel width. Each channel width is greater than the width or length of the pixel being addressed. By fabricating transistors with extremely long channel widths, lower mobility semiconductor materials can easily be used to fabricate the display device.

Electronic Device And Methods For Fabricating An Electronic Device

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US Patent:
7405424, Jul 29, 2008
Filed:
Mar 4, 2005
Appl. No.:
11/071305
Inventors:
Michael L. Chabinyc - Mountain View CA, US
Alberto Salleo - San Francisco CA, US
William S. Wong - San Carlos CA, US
Assignee:
Palo Alto Research Center Incorporated - Palo Alto CA
International Classification:
H01L 29/04
H01L 31/20
US Classification:
257 57, 257 59, 257347
Abstract:
An electronic device and a method of fabricating the electronic device includes forming a first electrical contact, a dielectric layer and a second electrical contact wherein the dielectric layer is located between the first and the second electrical contacts, forming an electrically insulating layer over the dielectric layer and the first electrical contact, exposing the first and second electrical contact, the dielectric layer and a first portion of the electrically insulating layer to radiation from the side of the first electrical contact, removing a second portion of the electrically insulating layer that was not irradiated by the radiation, providing a semiconductor material over a portion of the dielectric layer, and forming at least a third electrical contact over at least a portion of the electrically insulting layer and the semiconductor material.

Thin-Film Transistor Array With Ring Geometry

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US Patent:
7425734, Sep 16, 2008
Filed:
Jul 25, 2005
Appl. No.:
11/190178
Inventors:
William S. Wong - San Carlos CA, US
Jeng Ping Lu - Mountain View CA, US
Alberto Salleo - San Francisco CA, US
Michael L. Chabinyc - Mountain View CA, US
Raj B. Apte - Palo Alto CA, US
Robert A. Street - Palo Alto CA, US
Assignee:
Palo Alto Research Center Incorporated - Palo Alto CA
International Classification:
H01L 27/148
US Classification:
257222, 257225, 257257, 257290, 257443
Abstract:
An improved transistor array for a display or sensor device is described. The display or sensor device includes a plurality of pixels. Each pixel includes a width and a length. Each pixel is addressed by a transistor. The transistor addressing each pixel has a channel with a channel width. Each channel width is greater than the width or length of the pixel being addressed. By fabricating transistors with extremely long channel widths, lower mobility semiconductor materials can easily be used to fabricate the display device.

Micro-Machined Fuel Cells

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US Patent:
7459225, Dec 2, 2008
Filed:
Nov 24, 2003
Appl. No.:
10/722156
Inventors:
Raj B. Apte - Palo Alto CA, US
David G. Duff - Woodside CA, US
Christian G. Van de Walle - Sunnyvale CA, US
Jeng Ping Lu - Mountain View CA, US
Alberto Salleo - San Francisco CA, US
Stephen D. White - Santa Clara CA, US
International Classification:
H01M 8/10
US Classification:
429 30
Abstract:
An improved fuel cell is described. The invention addresses the problem of mechanical failure in thin electrolytes. One embodiment varies the thickness of the electrolyte and positions at least either the anode or cathode in the recessed region to provide a short travel distance for ions traveling from the anode to the cathode or from the cathode to the anode. A second embodiment uses a uniquely shaped manifold cover to allow close positioning of the anode to the cathode. Using the described structures results in a substantial improvement in fuel cell reliability and performance.
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Alberto Salleo from San Francisco, CA, age ~53 Get Report