Alan Ming Chen

8095765, Jan 10, 2012

Mar 4, 2009

12/397396

Mehdi Asnaashari - Danville CA, US
Alan Chen - Cupertino CA, US
Siamack Nemazie - Los Altos Hills CA, US

Micron Technology, Inc. - Boise ID

G06F 12/00

711170, 711103, 711159, 711202, 714 25, 714 45

Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes. Embodiments include determining defective blocks within the planes. If none of the blocks at a particular block position are determined to be defective, embodiments include assigning the blocks at the particular block position to a super block, and if one or more of the blocks at a particular block position are determined to be defective, embodiments include: assigning the blocks at the particular block position determined to be defective to a super block; and assigning a respective replacement block to the super block for each of the one or more blocks at the particular block position determined to be defective. The respective replacement block is selected from a number of blocks within a respective one of the planes that includes the respective block determined to be defective.

8239614, Aug 7, 2012

Mar 4, 2009

12/397402

Mehdi Asnaashari - Danville CA, US
Alan Chen - Cupertino CA, US
Siamack Nemazie - Los Altos Hills CA, US
Dale P. McNamara - San Jose CA, US

Micron Technology, Inc. - Boise ID

G06F 12/02

711103, 711170, 711E12008

The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.

8312245, Nov 13, 2012

Jan 10, 2012

13/347054

Mehdi Asnaashari - Danville CA, US
Alan Chen - Cupertino CA, US
Siamack Nemazie - Los Altos Hills CA, US

Micron Technology, Inc. - Boise ID

G06F 12/00

711170, 711103, 711159, 711202, 714 25, 714 45

One or more embodiments comprise control circuitry coupled to one or more memory devices having a number of planes of physical blocks organized into super blocks. The control circuitry can be configured to: determine defective physical blocks among the number of planes; responsive to none of the physical blocks at a particular block position being determined to be defective, assign the physical blocks at the particular block position to a super block; and responsive to one or more of the physical blocks at a particular block position being determined to be defective, assign non-defective physical blocks at the particular block position to a super block and assign a replacement physical block to the super block for the respective defective physical blocks at the particular block position, the replacement physical block selected from a number of physical blocks within a respective plane that includes a respective defective physical block.

20120303931, Nov 29, 2012

Aug 6, 2012

13/567680

Mehdi Asnaashari - Danville CA, US
Alan Chen - Cupertino CA, US
Siamack Nemazie - Los Altos Hills CA, US
Dale P. McNamara - San Jose CA, US

MICRON TECHNOLOGY, INC. - Boise ID

G06F 12/06

711209, 711E12078

The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.