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Al F Tasch

from Austin, TX
Age ~83

Al Tasch Phones & Addresses

  • 3208 Clear View Dr, Austin, TX 78703 (512) 476-5021 (512) 476-8102

Publications

Us Patents

High Mobility Heterojunction Transistor And Method

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US Patent:
63197995, Nov 20, 2001
Filed:
May 9, 2000
Appl. No.:
9/568091
Inventors:
Qiqing Ouyang - Austin TX
Al F. Tasch - Austin TX
Sanjay Kumar Banerjee - Austin TX
Assignee:
Board of Regents, The University of Texas System - Austin TX
International Classification:
H01L 21425
US Classification:
438528
Abstract:
A heterojunction transistor with high mobility carriers in the channel region includes a source region and a drain region formed in a semiconductor body with the source region and the drain region comprising doped semiconductor alloys separated from the substrate by heterojunctions. A channel region is provided between the source region and the drain region comprising an undoped layer of an alloy of the semiconductor material and a deposited layer of material of the semiconductor body overlying the undoped layer. A gate electrode is formed on a gate oxide over the channel region. In fabricating the high mobility heterojunction transistor, the spaced source and drain regions are formed in the substrate by implanting dopant of conductivity type opposite to the substrate and a material in the alloy and then annealing the structure to form the alloy of the semiconductor material under the undoped layer.

High Density Non-Charge-Sensing Dram Cell

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US Patent:
47631813, Aug 9, 1988
Filed:
Dec 8, 1986
Appl. No.:
6/938913
Inventors:
Al F. Tasch - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2978
US Classification:
357 236
Abstract:
A non-charge-sensing high density dynamic random access memory (DRAM) cell using a trench capacitor as a vertical FET and two active field effect transistors (FETs). A particular bit line is shared by the cells on either side of it; the bit line on one side of a particular cell being used to write to the cell while the bit line on the other side of the cell is used to read from the cell. This dual use of bit lines, plus the use of a vertical FET transistor along one side of a trench capacitor, plus the avoidance for the need of a relatively large storage capacitor since the cell is not read by "dumping" or releasing its charge onto the bit line all aid in making this cell compact and suitable for high density memories. Since the substrate serves as the second source/drain region of the vertical FET, a separate line for this region is eliminated, also contributing substantially to a smaller cell size.

Growth Of Polycrystalline Caf.sub.2 Via Low Temperature Omcvd

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US Patent:
50265750, Jun 25, 1991
Filed:
Jul 11, 1989
Appl. No.:
7/379016
Inventors:
Richard A. Jones - Austin TX
Alan H. Cowley - Austin TX
Al F. Tasch - Austin TX
Assignee:
Board of Regents, The University of Texas System - Austin TX
International Classification:
C23C 1630
C23C 1646
US Classification:
427255
Abstract:
The present invention involves the use of organocalcium precursors for the chemical vapor deposition of thin CaF. sub. 2 films under exceptionally mild conditions. This method is based on utilizing an organocalcium compound and a source of fluorine in a chemical vapor deposition reaction to form CaF. sub. 2.
Al F Tasch from Austin, TX, age ~83 Get Report