Akio Shigeeda

58025553, Sep 1, 1998

Mar 13, 1997

8/816460

Akio Shigeeda - Dallas TX

Texas Instruments Incorporated - Dallas TX

G06F 1300
G11C 11406

711106

A refresh controller circuit in an electronic device, such as a microprocessor unit of a portable computer adapted for docking into a docking station, and a method of operating a computer system to control a refresh operation, are disclosed. The refresh controller circuit includes a refresh clock circuit, a refresh queue counter circuit, and an idle condition detector responsive to the absence of memory read and write requests over a period of time. The refresh controller circuit also includes a latch for storing bits indicative of a self refresh mode enable and a refresh queuing enable. A suspend enable circuit is fed by an output of the idle condition detector and a stop request line, and a refresh request circuit is responsive to outputs of the refresh queue counter, the idle condition detector, and the refresh queuing enable. A refresh row address strobe (RAS) circuit has inputs from the self-refresh circuit and the suspend enable circuit. A RAS multiplexer has inputs for an output of the refresh RAS circuit and for data access RAS, and has an output connected to RAS output terminals of the memory controller for connection to an external dynamic random access memory to effect refresh.

57377480, Apr 7, 1998

Mar 15, 1995

8/404702

Akio Shigeeda - Dallas TX

Texas Instruments Incorporated - Dallas TX

G06F 1200
G06F 1300

711122

An electronic device for use in a computer system, and having a small second-level write-back cache, is disclosed. The device may be implemented into a single integrated circuit, as a microprocessor unit, to include a microprocessor core, a memory controller circuit, and first and second level caches. In a system implementation, the device is connected to external dynamic random access memory (DRAM). The first level cache is a write-through cache, while the second level cache is a write-back cache that is much smaller than the first level cache. In operation, a write access that is a cache hit in the second level cache writes to the second level cache, rather than to DRAM, thus saving a wait state. A dirty bit is set for each modified entry in the second level cache. Upon the second level cache being full of modified data, a cache flush to DRAM is automatically performed.

57130060, Jan 27, 1998

Jun 7, 1995

8/478163

Akio Shigeeda - Dallas TX

Texas Instruments Incorporated - Dallas TX

G06F 1214
G06F 1200

39549701

An electronic device and a method of operating the same to control access to configuration registers used by a memory controller, are disclosed. The disclosed device includes a single integrated circuit microprocessor unit that includes a microprocessor core, a memory controller circuit, a bus bridge circuit, and configuration registers. The microprocessor unit is connected to external dynamic random access memory (DRAM). The memory controller circuit is operable to perform an operation utilizing current information in one or more of the configuration registers. The bus bridge circuit includes a request logic circuit for supplying a request output signaling an impending access to one or more of the configuration registers. The memory controller circuit includes a reply logic circuit for supplying a reply output back to the request logic circuit after the operation utilizing current configuration register information is completed. The request logic includes an enable circuit responsive to the reply output to then enable the impending access to the configuration registers.

57245533, Mar 3, 1998

Jun 7, 1995

8/474850

Akio Shigeeda - Dallas TX

Texas Instruments Incorporated - Dallas TX

G06F 1200
G11C 800

39549701

An electronic system including circuitry for generating column addresses for a memory in the system, based upon signals on an address bus in the system, is disclosed. The disclosed system includes a microprocessor unit having a memory controller unit, within which circuitry for receiving address lines from the address bus, and for receiving control register bits indicating a particular memory array type, is provided. The memory array type indicates the number of the address bits which are to be forwarded to the memory as the column address, rather than as the row address. The memory is of a dynamic random access (DRAM) type, for which row and column addresses are time-multiplexed over the same lines. The microprocessor unit may be integrated onto a single integrated circuit chip with the memory controller, and may include a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes circuitry for controlling the access to configuration registers, and circuitry for determining the sizes of individual memory banks in the memory.

57377650, Apr 7, 1998

Jun 7, 1995

8/488350

Akio Shigeeda - Dallas TX

G06F 1300

711170

An electronic system, such as a computer system, in which access to configuration registers used by a memory controller, is selectively enabled. The disclosed system includes a single integrated circuit microprocessor unit that includes a microprocessor core, a memory controller circuit, a bus bridge circuit, and configuration registers. The microprocessor unit is connected to external dynamic random access memory (DRAM). The memory controller circuit is operable to perform an operation utilizing current information in one or more of the configuration registers. The bus bridge circuit includes a request logic circuit for supplying a request output signaling an impending access to one or more of the configuration registers. The memory controller circuit includes a reply logic circuit for supplying a reply output back to the request logic circuit after the operation utilizing current configuration register information is completed. The request logic includes an enable circuit responsive to the reply output to then enable the impending access to the configuration registers.

57377642, Apr 7, 1998

Jun 7, 1995

8/474582

Akio Shigeeda - Dallas TX

Texas Instruments Incorporated - Dallas TX

G06F 1200
G06F 1300

711170

A method and circuitry for generating column addresses for a memory based upon signals on an address bus in a computer system, are disclosed. The disclosed circuitry is provided within a memory controller unit of a microprocessor unit, and includes circuitry for receiving address lines from the address bus, and for receiving control register bits indicating a particular memory array type. The memory array type indicates the number of the address bits which are to be forwarded to the memory as the column address, rather than as the row address. The memory is of a dynamic random access memory (DRAM) type, for which row and column addresses are time-multiplexed over the same lines. The microprocessor unit may be integrated onto a single integrated circuit chip with the memory controller, and may include a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes circuitry for controlling the access to configuration registers, and circuitry for determining the sizes of individual memory banks in the memory.

57375631, Apr 7, 1998

Jun 7, 1995

8/472623

Akio Shigeeda - Dallas TX

Texas Instruments Incorporated - Dallas TX

G06F 1206
G06F 1200

395405

A method and circuitry for testing a memory in a computer system, to determine the sizes of individual memory banks, is disclosed. The disclosed circuitry is provided within a memory controller unit of a microprocessor unit, and includes circuitry for enabling the selection of an individual memory bank of a memory, such as dynamic random access memory, which is arranged as multiple banks of arbitrary size. In operation, a memory bank is selected, and a first data word is written to the bottom memory address of the bank (which, for banks other than the first bank, is the top memory address of the previous bank). A second data word is written to a second memory location that is spaced apart from the bottom address by a trial value of the bank size. If the trial bank size is too small, the second data word will not overwrite the bottom address; if the trial bank size is accurate, however, the second data word will overwrite the bottom address, following which a register entry is made for the selected bank to indicate that its top memory address is the bottom address plus the determined bank size. The microprocessor unit may be integrated onto a single integrated circuit chip with the memory controller, and may include a first level write-through cache in combination with a significantly smaller second level write-back cache.

57784256, Jul 7, 1998

Jun 7, 1995

8/484420

Akio Shigeeda - Dallas TX

Texas Instruments Incorporated - Dallas TX

G06F 1300

711122

An electronic system, such as a computer system, having a first level write through cache and a smaller second-level write-back cache, is disclosed. The disclosed computer system includes a single integrated circuit microprocessor unit that includes a microprocessor core, a memory controller circuit, and first and second level caches. The microprocessor unit is connected to external dynamic random access memory (DRAM). The first level cache is a write-through cache, while the second level cache is a write-back cache that is much smaller than the first level cache. In operation, a write access cache miss to the first level cache that is a cache hit in the second level cache effects a write to the second level cache, rather than to DRAM, thus saving a wait state. A dirty bit is set for each modified entry in the second level cache. Upon the second level cache being full of modified data, a cache flush to DRAM is automatically performed.