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Akash A Agrawal

from San Jose, CA
Age ~42
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Related to:
Mukesh K Agrawal, 53Neeraj M Agrawal, 41Meha AgrawalDheeraj M Agrawal, 42
Connected to:
Abhisek K Agrawal, 39Abhyudaya Agrawal, 47Anup Agrawal, 42Anupama Agrawal, 54Anurag Agrawal, 51Arpana Agrawal, 45Aruna K Agrawal, 58Ashok K Agrawala, 81Balkishan Agrawal, 74Bijay K Agrawal, 55

Akash Agrawal Phones & Addresses

  • San Jose, CA
  • 2515 E Red Cedar Ln APT 202, Boise, ID 83716
  • Sunnyvale, CA
  • Binghamton, NY
  • Ithaca, NY
  • Johnson City, NY

Work

Company: Micron technology inc May 2011 Position: Package simulation engineer

Education

School / High School: Binghamton University, State University of New York- New York, NY Jan 2007 Specialities: M.S. Me in Solid Mechanics

Skills

CAE Modeling: Pro/Engineer 2002 / Wildf... • Lansmont Drop System • MTS Applications: MS - Word • Excel • PowerPoint; MS Project; Adobe Photoshop...

Resumes

Resumes

Akash Agrawal Photo 1

Senior Manager, Packaging Architect

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Location:
San Jose, CA
Industry:
Mechanical Or Industrial Engineering
Work:
Amd
Smts, Packaging Engineer
Xperi Corporation Jun 2014 - Mar 2017
Senior Mechanical Simulation Engineer
Micron Technology Jun 2011 - Jun 2014
Package Simulation Engineer
Microsoft Feb 2010 - May 2011
Mechanical and Reliability Consultant
Binghamton University Jan 2007 - Dec 2009
Research Assistant
Education:
Binghamton University 2007 - 2009
Master of Science, Masters, Mechanical Engineering
Skills:
Finite Element Analysis
Simulations
Ansys
Solidworks
Engineering
Manufacturing
Product Development
Mechanical Engineering
Characterization
Matlab
Design For Manufacturing
Fmea
Electronics
Design of Experiments
Mems
Pro Engineer
Abaqus
Minitab
Autocad
Failure Analysis
Numerical Analysis
R&D
Modeling
Labview
Cae
Reliability Engineering
Cfd
Pcb Design
Root Cause Analysis
Reliability
Engineering Management
Thermal
Akash Agrawal Photo 2

Sr. Sql Developer At Asite

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Position:
Sr. SQL Developer at Asite
Location:
Ahmedabad, Gujarat, India
Industry:
Computer Software
Work:
Asite - Ahmedabad Area, India since Sep 2012
Sr. SQL Developer
Asite - Ahmedabad Area, India Aug 2011 - Oct 2012
SQL Developer
PETCO Animal Supplies, Inc. Mar 2010 - Apr 2011
Sr. SSIS Developer
Education:
South Gujarat University 2002 - 2006
B.E., Computer Engineering
Skills:
SQL Server
T-SQL
SSIS
SSRS
SSAS
ETL
Databases
Database Design
SQL database design
SQL
Microsoft SQL Server
Akash Agrawal Photo 3

Akash Agrawal

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Location:
United States
Akash Agrawal Photo 4

Akash Agrawal

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Location:
United States
Akash Agrawal Photo 5

Akash Agrawal

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Akash Agrawal Photo 6

Akash Agrawal

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Akash Agrawal Photo 7

Akash Agrawal

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Akash Agrawal Photo 8

Akash Agrawal

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Publications

Us Patents

Evaluating On-Device Machine Learning Model(S) Based On Performance Measures Of Client Device(S) And/Or The On-Device Machine Learning Model(S)

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US Patent:
20220309389, Sep 29, 2022
Filed:
Mar 29, 2021
Appl. No.:
17/215588
Inventors:
- Mountain View CA, US
Akash Agrawal - San Jose CA, US
Françoise Beaufays - Mountain View CA, US
Tamar Lucassen - Campbell CA, US
International Classification:
G06N 20/00
G06N 5/04
Abstract:
Implementations disclosed herein are directed to systems and methods for evaluating on-device machine learning (ML) model(s) based on performance measure(s) of client device(s) and/or the on-device ML model(s). The client device(s) can include on-device memory that stores the on-device ML model(s) and a plurality of testing instances for the on-device ML model(s). When certain condition(s) are satisfied, the client device(s) can process, using the on-device ML model(s), the plurality of testing instances to generate the performance measure(s). The performance measure(s) can include, for example, latency measure(s), memory consumption measure(s), CPU usage measure(s), ML model measure(s) (e.g., precision and/or recall), and/or other measures. In some implementations, the on-device ML model(s) can be activated (or kept active) for use locally at the client device(s) based on the performance measure(s). In other implementations, the on-device ML model(s) can be sparsified based on the performance measure(s).

Bonding Of Laminates With Electrical Interconnects

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US Patent:
20190221510, Jul 18, 2019
Filed:
Mar 21, 2019
Appl. No.:
16/361116
Inventors:
- San Jose CA, US
Belgacem Haba - Saratoga CA, US
Wael Zohni - Campbell CA, US
Liang Wang - Newark CA, US
Akash Agrawal - San Jose CA, US
Assignee:
Invensas Corporation - San Jose CA
International Classification:
H01L 23/498
H01L 21/48
H01L 23/00
Abstract:
A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.

Bonding Of Laminates With Electrical Interconnects

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US Patent:
20180114747, Apr 26, 2018
Filed:
Oct 26, 2016
Appl. No.:
15/334606
Inventors:
- San Jose CA, US
Belgacem Haba - Saratoga CA, US
Wael Zohni - San Jose CA, US
Liang Wang - Milpitas CA, US
Akash Agrawal - San Jose CA, US
Assignee:
Invensas Corporation - San Jose CA
International Classification:
H01L 23/498
H01L 21/48
H01L 23/00
Abstract:
A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.

Multi-Surface Edge Pads For Vertical Mount Packages And Methods Of Making Package Stacks

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US Patent:
20180040544, Feb 8, 2018
Filed:
Jul 26, 2017
Appl. No.:
15/660718
Inventors:
- San Jose CA, US
Min Tao - San Jose CA, US
Javier A. Delacruz - San Jose CA, US
Hoki Kim - Santa Clara CA, US
Akash Agrawal - San Jose CA, US
Assignee:
Invensas Corporation - San Jose CA
International Classification:
H01L 23/498
H05K 3/34
H05K 1/18
H05K 1/11
H01L 25/10
H01L 21/48
Abstract:
Multi-surface edge pads for vertical mount packages and methods of making package stacks are provided. Example substrates for vertical surface mount to a motherboard have multi-surface edge pads. The vertical mount substrates may be those of a laminate-based FlipNAND. The multi-surface edge pads have cutouts or recesses that expose more surfaces and more surface area of the substrate for bonding with the motherboard. The cutouts in the edge pads allow more solder to be used between the attachment surface of the substrate and the motherboard. The placement and geometry of the resulting solder joint is stronger and has less internal stress than conventional solder joints for vertical mounting. In an example process, blind holes can be drilled into a thickness of a substrate, and the blind holes plated with metal. The substrate can be cut in half though the plated holes to provide two substrates with plated multi-surface edge pads including the cutouts for mounting to the motherboard.

Fan-Out Wafer-Level Packaging Using Metal Foil Lamination

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US Patent:
20170170031, Jun 15, 2017
Filed:
Feb 27, 2017
Appl. No.:
15/443371
Inventors:
- San Jose CA, US
Rajesh Katkar - San Jose CA, US
Long Huynh - Santa Clara CA, US
Laura Wills Mirkarimi - Sunol CA, US
Bongsub Lee - Mountain View CA, US
Gabriel Z. Guevara - San Jose CA, US
Tu Tam Vu - San Jose CA, US
Kyong-Mo Bang - Fremont CA, US
Akash Agrawal - San Jose CA, US
Assignee:
Invensas Corporation - San Jose CA
International Classification:
H01L 21/56
H01L 21/683
H01L 21/768
H01L 25/00
H01L 21/304
H01L 23/29
H01L 25/065
H01L 21/02
H01L 23/00
Abstract:
Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

Fan-Out Wafer-Level Packaging Using Metal Foil Lamination

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US Patent:
20170103957, Apr 13, 2017
Filed:
Oct 7, 2015
Appl. No.:
14/877205
Inventors:
- San Jose CA, US
Rajesh Katkar - San Jose CA, US
Long Huynh - Santa Clara CA, US
Laura Wills Mirkarimi - Sunol CA, US
Bongsub Lee - Mountain View CA, US
Gabriel Z. Guevara - San Jose CA, US
Tu Tam Vu - San Jose CA, US
Kyong-Mo Bang - Fremont CA, US
Akash Agrawal - San Jose CA, US
Assignee:
Invensas Corporation - San Jose CA
International Classification:
H01L 23/00
H01L 21/683
H01L 23/29
H01L 21/56
H01L 21/304
H01L 23/538
H01L 21/02
H01L 21/768
Abstract:
Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

Integrated Circuit Assemblies With Rigid Layers Used For Protection Against Mechanical Thinning And For Other Purposes, And Methods Of Fabricating Such Assemblies

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US Patent:
20170084539, Mar 23, 2017
Filed:
Nov 30, 2016
Appl. No.:
15/364534
Inventors:
- San Jose CA, US
Cyprian Emeka UZOH - San Jose CA, US
Charles G. WOYCHIK - San Jose CA, US
Hong SHEN - Palo Alto CA, US
Arkalgud R. SITARAM - Cupertino CA, US
Liang WANG - Milpitas CA, US
Akash AGRAWAL - San Jose CA, US
Rajesh KATKAR - San Jose CA, US
Assignee:
Invensas Corporation - San Jose CA
International Classification:
H01L 23/538
H01L 23/31
H01L 21/48
Abstract:
Die () and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer () or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (). Then the interposer is thinned from below. Before encapsulation, a layer () more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

Wafer-Level Packaging Using Wire Bond Wires In Place Of A Redistribution Layer

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US Patent:
20170069591, Mar 9, 2017
Filed:
Nov 21, 2016
Appl. No.:
15/357553
Inventors:
- San Jose CA, US
Tu Tam Vu - San Jose CA, US
Bongsub Lee - Mountain View CA, US
Kyong-Mo Bang - Fremont CA, US
Xuan Li - Santa Clara CA, US
Long Huynh - Santa Clara CA, US
Gabriel Z. Guevara - San Jose CA, US
Akash Agrawal - San Jose CA, US
Willmar Subido - San Jose CA, US
Laura Wills Mirkarimi - Sunol CA, US
Assignee:
Invensas Corporation - San Jose CA
International Classification:
H01L 23/00
H01L 25/065
H01L 21/78
H01L 25/10
H01L 23/31
H01L 21/56
Abstract:
An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.
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Akash A Agrawal from San Jose, CA, age ~42 Get Report