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Ajoy Aswadhati Phones & Addresses

  • San Jose, CA
  • Livermore, CA
  • 1674 Quail Ave, Sunnyvale, CA 94087 (408) 244-6044
  • 11766 Pine Brook Ct, Cupertino, CA 95014 (408) 564-4960 (408) 255-1132
  • Dallas, TX
  • Santa Clara, CA
  • Fremont, CA
  • 11766 Pine Brook Ct, Cupertino, CA 95014 (408) 255-1132

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Emails

Business Records

Name / Title
Company / Classification
Phones & Addresses
Ajoy Aswadhati
President
LUCID SOLUTIONS, INC
11766 Pne Brk Ct, Cupertino, CA 95014

Publications

Us Patents

Spi-4.2 Dynamic Implementation Without Additional Phase Locked Loops

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US Patent:
7650525, Jan 19, 2010
Filed:
Oct 3, 2006
Appl. No.:
11/538157
Inventors:
Peter Chang - Fremont CA, US
Amrik Bains - Livermore CA, US
Ajoy Aswadhati - Cupertino CA, US
Edward Wang - Palo Alto CA, US
Assignee:
Force 10 Networks, Inc. - San Jose CA
International Classification:
G06F 1/00
US Classification:
713500, 713501, 375371, 375354
Abstract:
A method and apparatus for receiving clocked data signals such as SPI-4. 2 data signals is described. In one embodiment, each data signal lane is deskewed with respect to the clock by oversampling the signal on that lane, and considering multiple versions of a data sequence at different temporal offsets to the clock for correct reception of a training sequence. One of the temporal offsets is subsequently selected to provide the received bit sequence for that lane. Other embodiments are described and claimed.

Multi-Port Network Device Using Lookup Cost Backpressure

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US Patent:
8027256, Sep 27, 2011
Filed:
Jun 2, 2005
Appl. No.:
11/142998
Inventors:
Krishnamurthy Subramanian - Mountain View CA, US
Amrik Baines - Livermore CA, US
Manu Thomas - Milpitas CA, US
Jason Lee - Palo Alto CA, US
Ajoy Aswadhati - Cupertino CA, US
Assignee:
Force 10 Networks, Inc. - San Jose CA
International Classification:
G01R 31/08
H04J 1/16
US Classification:
370231, 370235, 370237
Abstract:
In one embodiment of a network device, multiple packet sources contend for access to a packet processing pipeline. The packet processing pipeline tracks the usage of lookup resources by each of the multiple packet sources. When a packet source is detected to be using more than an acceptable allocation of the lookup resources, access to the packet processing pipeline for that source is limited or curtailed to bring that source back within an acceptable allocation of resources. This backpressure mechanism can be used to control sources that, although within a bandwidth limit, are submitting a packet type mix that is consuming unfair percentages of lookup resources in an oversubscribed system. Other embodiments are described and claimed.

Non-Stop Voip Support

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US Patent:
8514712, Aug 20, 2013
Filed:
Dec 2, 2008
Appl. No.:
12/315372
Inventors:
Ajoy Aswadhati - Cupertino CA, US
Assignee:
Force10 Networks, Inc. - San Jose CA
International Classification:
G01R 31/08
G06F 11/00
G08C 15/00
H04J 1/16
H04J 3/14
H04L 1/00
H04L 12/26
US Classification:
370235, 370352, 370356, 370390, 726 22
Abstract:
A packet switch collects configuration information on the peer devices to which it connects. Peer devices that are IP (Internet Protocol) telephones are sensed. Such devices may also bridge packets to a connected device such as a computer, but with a bridge capability that cannot handle large broadcast storms on the network. The packet switch uses the configuration information to limit broadcast storms on its ports connected to the relatively fragile IP telephones/bridges. This can prevent broadcast storms from disrupting calls on the IP telephones connected to the packet switch.

Pipelined Network Processing With Fifo Queues

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US Patent:
20040088439, May 6, 2004
Filed:
Oct 31, 2002
Appl. No.:
10/286361
Inventors:
Eugene Lee - San Jose CA, US
Cong Ye - Fremont CA, US
Peter Chang - Fremont CA, US
Ajoy Aswadhati - Cupertino CA, US
International Classification:
G06F015/16
US Classification:
709/250000
Abstract:
A system and method for operating on data within a network device is described. Between two data operations in a network device is a FIFO queue, which is used to separate the clock domains of the data operations. Data from the first operation is stored in the FIFO queue, which signals an indication to the second operation that there is data in the queue. When the second operation is signaled that there is data in the FIFO queue, it immediately begins reading data from the queue, and begins performing its prescribed operations on the data once it has read enough data from the queue for it to begin operating.

Solid State Drive Architecture

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US Patent:
20120102263, Apr 26, 2012
Filed:
Oct 24, 2011
Appl. No.:
13/280206
Inventors:
Ajoy Aswadhati - Cupertino CA, US
Assignee:
FASTOR SYSTEMS, INC. - Dublin CA
International Classification:
G06F 12/02
US Classification:
711103, 711E12008
Abstract:
Embodiments of apparatuses, methods and systems of solid state drive are disclosed. One embodiment of a solid state drive includes a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory. Further, this embodiment includes a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information. The scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory.

Fabric-Based Solid State Drive Architecture

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US Patent:
20130275835, Oct 17, 2013
Filed:
Mar 15, 2013
Appl. No.:
13/831816
Inventors:
Ajoy Aswadhati - Cupertino CA, US
International Classification:
G06F 11/10
US Classification:
714773, 711103
Abstract:
Embodiments of apparatus, methods and systems of solid state drive are disclosed. One embodiment of a solid state drive includes a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory. Further, this embodiment includes a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information. The scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory.
Ajoy Kumar Aswadhati from San Jose, CA, age ~62 Get Report