Search

Ajay A Saproo

from Los Altos, CA
Age ~55
Get Report
Also known as:
Ajay N Saproo, Ajay S Saproo, Ajay C Saproo, Saproo Saproo, Ajay Ajay, Ajay Null, Saproo Ajay
Phone and address:
654 Berry Ave, Los Altos, CA 94024
Related to:
Mihika L SapruVicky Raina SaprooKanti Saproo
Connected to:
Rohit Sapru, 44Michael J Sapsara, 78Paul S Sapsara, 92Rachel Sapsford, 55Jason W Sapsin, 55Yefim Sapson, 69Dipti M Sapte, 42Sachin D Sapte, 49Anitra L Sapula, 125Victor Sapuppo, 86

Ajay Saproo Phones & Addresses

  • 654 Berry Ave, Los Altos, CA 94024
  • 536 Palmer Ln, Menlo Park, CA 94025 (650) 323-2730
  • 3628 Madison Cmn, Fremont, CA 94538 (510) 623-2326
  • 3625 Madison Cmn, Fremont, CA 94538
  • 500 W Middlefield Rd #160, Mountain View, CA 94043 (650) 969-2715
  • Cincinnati, OH
  • Fremont, OH
  • Santa Clara, CA

Work

Company: Miasole Aug 2008 Position: Director, process integration and reliability

Education

School / High School: UNIVERSITY OF CINCINNATI- Cincinnati, OH 1994 Specialities: Master of Science in Electrical Engineering

Skills

Engineering and Technology Management ... • Reliability Engineering Problem Solv... • Design of Experiments • Statistical Analysis (JMP) Financial... • Semiconductor Capital Equipment • Photovoltaics • Thin Film Solar Chemical Vapor Depos... • Physical Vapor Deposition (PVD • Sputtering) • Plasma Etch

Resumes

Resumes

Ajay Saproo Photo 1

Founder And Chief Executive Officer

View page
Location:
San Francisco, CA
Industry:
Renewables & Environment
Work:
Clear Sky Analytics
Founder and Chief Executive Officer
Sunedison Nov 2014 - Jan 2017
Head, Reliability and Energy Analysis
Miasole Aug 2008 - Nov 2014
Director, Process Integration and Reliability
Lam Research Dec 2007 - Aug 2008
Technical Director
Lam Research Aug 2007 - Dec 2007
Consultant
Education:
Cfa Institute 2006
University of Cincinnati 1991 - 1994
Master of Science, Masters, Electronics Engineering Birla Institute of Technology and Science, Pilani 1987 - 1991
Bachelor of Engineering, Bachelors, Electronics Engineering
Skills:
Semiconductors
Photovoltaics
Design of Experiments
Engineering Management
Failure Analysis
Thin Films
Process Engineering
Cross Functional Team Leadership
Product Development
R&D
Jmp
Plasma Processing
Solar Energy
Process Simulation
Semiconductor Industry
Statistical Data Analysis
Reliability Engineering
Program Management
Manufacturing
Spc
Process Development
Start Ups
Semiconductor Equipment
Financial Analysis
Financial Modeling
Business Process Improvement
Process Integration
Continuous Improvement
Data Analysis
Research and Development
Problem Solving
Pvd
Cvd
Cleantech
Financial Statement Analysis
Financial Strategy
Business Strategy
Manufacturing Operations Management
Thin Film Solar
Chemical Vapor Deposition
Physical Vapor Deposition
Plasma Etch
Semiconductor Processing
Vacuum Technology
Fmea
Languages:
Hindi
Ajay Saproo Photo 2

Ajay Saproo

View page
Ajay Saproo Photo 3

Ajay Saproo Los Altos, CA

View page
Work:
MIASOLE

Aug 2008 to 2000
Director, Process Integration and Reliability
LAM RESEARCH CORPORATION

Dec 2007 to Aug 2008
Technical Director
LAM RESEARCH CORPORATION

Sep 2007 to Dec 2007
Consultant
JPMORGAN CHASE
San Francisco, CA
May 2006 to Jul 2007
Associate Analyst, Equity Research
NOVELLUS SYSTEMS

2005 to 2006
Senior Manager, PVD Modules
NOVELLUS SYSTEMS

2002 to 2004
Senior Manager, Product Development
NOVELLUS SYSTEMS

2001 to 2002
Manager, 300mm Process Development
NOVELLUS SYSTEMS

1999 to 2001
Technologist
Advanced R&D

1997 to 1999
Senior Process Engineer
LAM RESEARCH CORPORATION
Fremont, CA
Jan 1995 to Nov 1997
Process Engineer
Education:
UNIVERSITY OF CINCINNATI
Cincinnati, OH
1994
Master of Science in Electrical Engineering
BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE
Pilani, Rajasthan
1991
Bachelor of Science in Electrical Engineering
Skills:
Engineering and Technology Management Process Development Product Development Process Integration, Reliability Engineering Problem Solving Data Analysis, Design of Experiments, Statistical Analysis (JMP) Financial Analysis and Modeling Business Strategy Business Process Improvement Semiconductors, Semiconductor Capital Equipment, Photovoltaics, Thin Film Solar Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD, Sputtering), Plasma Etch

Publications

Us Patents

Predictive Wafer Temperature Control System And Method

View page
US Patent:
6468384, Oct 22, 2002
Filed:
Nov 9, 2000
Appl. No.:
09/710083
Inventors:
Vikram Singh - Fremont CA
Robert J. Whiting - Santa Clara CA
Paul K. Shufflebotham - San Jose CA
Ajay Saproo - Mountain View CA
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
C23F 100
US Classification:
15634527, 15634524, 118723 E
Abstract:
The present invention provides plasma processing systems and methods for providing a set-point temperature for substrates during plasma processing by controlling clamping force or RF power. The plasma processing system includes a plasma chamber, a controller, and an electrostatic power supply. The plasma chamber is arranged to receive an RF power and a source gas for producing plasma. The plasma chamber includes an electrostatic chuck for clamping a substrate in place during plasma processing. The electrostatic chuck includes an electrode and a sensor, which is arranged to monitor temperature of the substrate being processed. The controller is coupled to the sensor to receive the substrate temperature and is configured to generate a control signal for driving the substrate temperature to the set-point temperature. The electrostatic power supply is coupled between the controller and the electrode in the electrostatic chuck. The electrostatic power supply receives the control signal from the controller and generates a voltage adapted to clamp the substrate with a clamping force.

Annealing Process For Low-K Dielectric Film

View page
US Patent:
62969064, Oct 2, 2001
Filed:
Sep 30, 1999
Appl. No.:
9/410171
Inventors:
Jim Stimmell - San Jose CA
Joe Laia - Morgan Hill CA
Ajay Saproo - Mountain View CA
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
B05D 302
H01L 2131
US Classification:
427377
Abstract:
Dielectric films in integrated circuits are annealed in the presence of water to improve their thermal stability and their resistance to damage from ultraviolet radiation.

Method For Preparing Nitrogen Surface Treated Fluorine Doped Silicon Dioxide Films

View page
US Patent:
58691499, Feb 9, 1999
Filed:
Jun 30, 1997
Appl. No.:
8/886148
Inventors:
Dean R. Denison - San Jose CA
Ajay Saproo - Mountain View CA
David T. Hodul - Oakland CA
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
B05D 306
US Classification:
427579
Abstract:
A process of preparing a moisture-resistant fluorine containing SiO. sub. x film includes steps of supplying reactant gases containing silicon, oxygen and fluorine into a process chamber and generating plasma in the process chamber, supporting a substrate on a substrate support in the process chamber, depositing a fluorine-containing SiO. sub. x film on the substrate by contacting the substrate with the plasma while maintaining temperature of the film above 300. degree. C. , and nitriding an exposed surface of the film with a high density plasma. The silicon and fluorine reactants can be supplied by separate gases such as SiH. sub. 4 and SiF. sub. 4 or as a single SiF. sub. 4 gas and the oxygen reactant can be supplied by a pure oxygen gas. The SiH. sub. 4 and SiF. sub. 4 can be supplied in a ratio of SiH. sub. 4 /(SiH. sub. 4 +SiF. sub. 4) of no greater than 0. 5.

Photovoltaic Cell With High Efficiency Cigs Absorber Layer With Low Minority Carrier Lifetime And Method Of Making Thereof

View page
US Patent:
20180337294, Nov 22, 2018
Filed:
Jul 12, 2018
Appl. No.:
16/034131
Inventors:
- BEIJING, CN
Alex Austin - Carmel Valley CA, US
Robert Tas - Aromas CA, US
Neil Mackie - Fremont CA, US
Mats Larsson - Sunnyvale CA, US
Korhan Demirkan - Santa Clara CA, US
Weijie Zhang - San Jose CA, US
Jochen Titus - Sunnyvale CA, US
Robert Zubeck - Los Altos CA, US
Randy Dorn - Santa Clara CA, US
Asit Rairkar - San Jose CA, US
Ron Rulkens - Milpitas CA, US
Ajay Saproo - Los Altos CA, US
Dan Vitkavage - San Jose CA, US
International Classification:
H01L 31/0224
H01L 31/032
H01L 31/0392
H01L 31/0749
Abstract:
A solar cell containing a plurality of CIGS absorber sublayers has a conversion efficiency of at least 13.4 percent and a minority carrier lifetime below 2 nanoseconds. The sublayers may have a different composition from each other.
Control profile
Ajay A Saproo from Los Altos, CA, age ~55 Get Report