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Aidan F Shori

from Austin, TX
Age ~46
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Also known as:
Aidan Sheri, Shari Aiden
Phone and address:
2001 Mistywood Dr, Austin, TX 78746
Related to:
Rita ShoriFred Shori, 53Thomas W Dunnam, 74Kimberly A Ebner, 45Angiee DunnamAaron Shori, 49Angela Dunnam, 49James R Jones, 71Adrian ShoriThomas DunnamCarol A Dunnam, 74Audrey Shori
Connected to:
Ritu Shori, 45Jeffrey S Shorkey, 51Justin Shorkey, 82David J Shorma, 54William J Shorma, 69Gary D Shorman, 67Michael Shorman, 38Jay L Shorney, 71Alicia N Shorr, 34Bonnie D Shorr, 61

Aidan Shori Phones & Addresses

  • 2001 Mistywood Dr, Austin, TX 78746
  • Colton, TX
  • Allen, TX
  • Plano, TX
  • 4500 Burbank Dr, Baton Rouge, LA 70820

Work

Company: Intel corporation Aug 2019 Position: Mission control

Education

Degree: Masters, Master of Science In Electrical Engineering School / High School: Louisiana State University Aug 2000 to Dec 2003 Specialities: Electrical Engineering, Management

Skills

Cmos • Ic • Physical Design • Mixed Signal • Semiconductors • Verilog • Processors • Cadence Virtuoso • Vlsi • Silicon • Dram • Soc • Asic • Circuit Design • Analog • Low Power Design • Eda • Application Specific Integrated Circuits • Integrated Circuit Design • Debugging • Project Management • Project Planning • Management • Program Management • Project Engineering • Team Management • Risk Management • Product Management • Convincing People • Leadership • Team Leadership • Cross Functional Team Leadership • Strategic Leadership • Collaborative Leadership • Public Speaking • Influence Others • Strategic Influence • Influence at All Levels • Influential Communicator • Team Motivation • Performance Motivation • Performance Management • Performance Improvement • High Performance Teams • Cpu Design • Debuggers • Planning • Strategic Planning • Event Planning • Workforce Planning

Industries

Semiconductors

Resumes

Resumes

Aidan Shori Photo 1

Component Debug Project Manager And Site Lead

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Intel Corporation
Mission Control
Intel Corporation
Component Debug Project Manager and Site Lead
Intel Corporation Aug 2011 - Jan 2013
Circuit Designer
Micron Inc Apr 2004 - Jul 2011
Dram Designer
Education:
Louisiana State University Aug 2000 - Dec 2003
Masters, Master of Science In Electrical Engineering, Electrical Engineering, Management Simon Fraser University Aug 1996 - Aug 2000
Bachelors, Bachelor of Science, Applied Physics
Skills:
Cmos
Ic
Physical Design
Mixed Signal
Semiconductors
Verilog
Processors
Cadence Virtuoso
Vlsi
Silicon
Dram
Soc
Asic
Circuit Design
Analog
Low Power Design
Eda
Application Specific Integrated Circuits
Integrated Circuit Design
Debugging
Project Management
Project Planning
Management
Program Management
Project Engineering
Team Management
Risk Management
Product Management
Convincing People
Leadership
Team Leadership
Cross Functional Team Leadership
Strategic Leadership
Collaborative Leadership
Public Speaking
Influence Others
Strategic Influence
Influence at All Levels
Influential Communicator
Team Motivation
Performance Motivation
Performance Management
Performance Improvement
High Performance Teams
Cpu Design
Debuggers
Planning
Strategic Planning
Event Planning
Workforce Planning

Publications

Us Patents

System And Method For Synchronizing Asynchronous Signals Without External Clock

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US Patent:
7936637, May 3, 2011
Filed:
Jun 30, 2008
Appl. No.:
12/165257
Inventors:
Aidan Shori - Plano TX, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 8/00
US Classification:
3652331, 36523312
Abstract:
One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an internal clock signal provided by an internal clock generator. The internal clock generator may be enabled upon detecting inputs on the one or more asynchronous signals, and disabled once the one or more asynchronous inputs are synchronized with the internal clock signal. Thus, the internal clock signal is provided only for a duration required to synchronize the one or more asynchronous signals. Embodiments of the asynchronous synchronization device, as disclosed herein, may be implemented in a processor-based device and/or a memory device.

Memory Bank Signal Coupling Buffer And Method

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US Patent:
8400809, Mar 19, 2013
Filed:
Mar 24, 2011
Appl. No.:
13/071303
Inventors:
Aidan Shori - Plano TX, US
Sumit Chopra - Richardson TX, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 5/06
US Classification:
365 63, 36518917, 36518905, 36523003
Abstract:
A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

System And Method For Synchronizing Asynchronous Signals Without External Clock

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US Patent:
8559263, Oct 15, 2013
Filed:
May 2, 2011
Appl. No.:
13/099133
Inventors:
Aidan Shori - Plano TX, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 8/00
US Classification:
3652331, 36523312
Abstract:
One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an internal clock signal provided by an internal clock generator. The internal clock generator may be enabled upon detecting inputs on the one or more asynchronous signals, and disabled once the one or more asynchronous inputs are synchronized with the internal clock signal. Thus, the internal clock signal is provided only for a duration required to synchronize the one or more asynchronous signals. Embodiments of the asynchronous synchronization device, as disclosed herein, may be implemented in a processor-based device and/or a memory device.

Memory Bank Signal Coupling Buffer And Method

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US Patent:
20100177571, Jul 15, 2010
Filed:
Jan 14, 2009
Appl. No.:
12/353661
Inventors:
Aidan Shori - Plano TX, US
Sumit Chopra - Richardson TX, US
Assignee:
MICRON TECHNOLOGY, INC. - Boise ID
International Classification:
G11C 7/00
G11C 8/00
H03L 5/00
US Classification:
36518905, 365189011, 36523003, 327108, 365203
Abstract:
A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.
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Aidan F Shori from Austin, TX, age ~46 Get Report