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Aelan Mosden

from Castleton on Hudson, NY
Age ~52
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Also known as:
Allen Mosden, Mosden Aelan
Related to:
Robert L Daniels, 78Lizze SakBarbara A Muszel, 53Sam Muszel, 77Jayleen Leon, 40Nira Mosden, 88Fuad Fred Mosden, 90Sharon L Muszel, 49Norma E Hernandez, 81Brian Muszel, 46Ismael S Hernandez, 92Sarah Mosden, 29Richard A Daniels, 80
Connected to:
Sabine Mosdorfer, 57Alden K Mose, 97Bryan M Mose, 41Danielle Mose, 34Iosefa I Mose, 59Kyle R Mose, 34Nancy A Mose, 80Rayna Mose, 47Roget L Mose, 48Ryan D Mose, 41

Aelan Mosden Phones & Addresses

  • Castleton on Hudson, NY
  • 3 Justbrand Ln, Poughkeepsie, NY 12603 (845) 486-0282
  • La Grange, NY
  • 10813 Gambril Dr, Manassas, VA 20109
  • Wappingers Falls, NY
  • New Hyde Park, NY

Work

Company: Tokyo electron Sep 1, 2013 Position: Process engineering manager

Education

Degree: Bachelors, Bachelor of Science School / High School: Columbia University In the City of New York 1991 to 1995 Specialities: Chemical Engineering

Skills

Semiconductor Industry • Semiconductors • Thin Films • Design of Experiments • Metrology • Spc • Cvd • Electronics • Failure Analysis • Manufacturing • Silicon • Process Integration • Ic • Product Engineering • Characterization • R&D • Engineering Management • Pvd • Field Service • Process Simulation • Nanotechnology • Lithography • Microelectronics • Yield • Statistical Process Control • Cmos • Mems • Materials Science • Semiconductor Process • Photolithography • Jmp • Optics • Scanning Electron Microscopy • Atomic Layer Deposition • Integrated Circuits • Physical Vapor Deposition

Industries

Semiconductors

Resumes

Resumes

Aelan Mosden Photo 1

Process Engineering Manager

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Location:
3 Justbrand Ln, Poughkeepsie, NY 12603
Industry:
Semiconductors
Work:
Tokyo Electron
Process Engineering Manager
Tokyo Electron Jul 2005 - Sep 2013
Product Specialist
Tokyo Electron Dec 1995 - Jun 2005
Process Engineer
Education:
Columbia University In the City of New York 1991 - 1995
Bachelors, Bachelor of Science, Chemical Engineering
Skills:
Semiconductor Industry
Semiconductors
Thin Films
Design of Experiments
Metrology
Spc
Cvd
Electronics
Failure Analysis
Manufacturing
Silicon
Process Integration
Ic
Product Engineering
Characterization
R&D
Engineering Management
Pvd
Field Service
Process Simulation
Nanotechnology
Lithography
Microelectronics
Yield
Statistical Process Control
Cmos
Mems
Materials Science
Semiconductor Process
Photolithography
Jmp
Optics
Scanning Electron Microscopy
Atomic Layer Deposition
Integrated Circuits
Physical Vapor Deposition

Publications

Us Patents

Method Of Etching High Aspect Ratio Features

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US Patent:
7226868, Jun 5, 2007
Filed:
Oct 31, 2002
Appl. No.:
10/492541
Inventors:
Aelan Mosden - Poughkeepsie NY, US
Sandra Hyland - Falls Church VA, US
Minori Kajimoto - Kanagawa, JP
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
H01L 21/302
US Classification:
438710, 438706, 438714, 216 67
Abstract:
A plasma processing system for and method of utilizing an improved etch chemistry for effectively etching high aspect ratio silicon features. The process chemistry employs precursor gases suitable for producing a fluorine/chlorine etch chemistry as well as precursor gases suitable for forming chemical bonds of sufficient strength to create stable feature side-walls. The improved process chemistries include SO/SF/SiCl, SO/SF/Cl, SO/SiF/SiCl, SOSIF/Cl, O/F/Cl, N2/Cl, and NO/F/Cl-based chemistries.

Method And System For Treating A Hard Mask To Improve Etch Characteristics

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US Patent:
7291446, Nov 6, 2007
Filed:
Mar 17, 2004
Appl. No.:
10/801571
Inventors:
Aelan Mosden - Poughkeepsie NY, US
Dung Phan - Hyde Park NY, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
G03F 7/26
US Classification:
430316, 430317
Abstract:
During pattern transfer to a film stack, the hard mask layer, such as a tunable etch resistant antireflective coating (TERA), is consumed when etching the underling layer(s), leading to reduced etch performance and potential damage to the underlying layer(s), such as lack of profile control. A method of and system for preparing a structure on a substrate is described comprising: preparing a film stack comprising a thin film, a hard mask formed on the thin film, and a layer of light-sensitive material formed on the hardmask; forming a pattern in the layer of light-sensitive material; transferring the pattern to the hard mask; removing the layer of light-sensitive material; treating the surface layer of the hard mask in order to modify the surface; and transferring the pattern to the thin film.

System And Method Of Removing Chamber Residues From A Plasma Processing System In A Dry Cleaning Process

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US Patent:
7959970, Jun 14, 2011
Filed:
Mar 31, 2004
Appl. No.:
10/813390
Inventors:
Marcel Gaudet - Beacon NY, US
Aelan Mosden - Poughkeepsie NY, US
Robert J. Soave - LaGrangeville NY, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
C23C 16/00
US Classification:
4272481, 42725528, 42725531, 118715
Abstract:
A system and method is provided for removing chamber residues from a plasma processing system in a dry cleaning process. The dry cleaning process includes introducing a process gas including a gas containing carbon and oxygen in a process chamber of the plasma processing system, generating a plasma from the process gas, exposing the chamber residue to the plasma in a dry cleaning process to form a volatile reaction product, and exhausting the reaction product from the process chamber. The plasma processing system may be monitored to determine status of the processing system, and based upon the status from the monitoring, the method includes either continuing the exposing and monitoring, or stopping the dry cleaning process. The dry cleaning process can be a waferless dry cleaning (WDC) process, or a substrate may present on the substrate holder in the process chamber during the dry cleaning process.

Method And System For Deep Trench Silicon Etch

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US Patent:
20040256353, Dec 23, 2004
Filed:
Apr 9, 2004
Appl. No.:
10/821201
Inventors:
Siddhartha Panda - Beacon NY, US
Aelan Mosden - Poughkeepsie NY, US
Richard Wise - New Windsor NY, US
Kenro Sugiyama - Cambridge MA, US
Joseph Camilleri - Wappingers Falls NY, US
International Classification:
H01B013/00
C23C014/00
C23C014/32
US Classification:
216/018000
Abstract:
A method and system for deep trench silicon etch is presented. The method comprises introducing a reactive process gas and a Noble gas to a plasma processing system, wherein the reactive process gas comprises two or more of HBr, a fluorine-containing gas, and O, and the Noble gas comprises at least one of He, Ne, Ar, Xe, Kr, and Rn. Additionally, radio frequency (RF) power is applied to the substrate holder, upon which the substrate rests, at two different frequencies. The first RF frequency is greater than MHz, and the second frequency is less than MHz.

Replacing Chamber Components In A Vacuum Environment

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US Patent:
20050205209, Sep 22, 2005
Filed:
Mar 18, 2004
Appl. No.:
10/803805
Inventors:
Aelan Mosden - Poughkeepsie NY, US
International Classification:
C23F001/00
US Classification:
156345310, 118719000, 156915000
Abstract:
An apparatus and method are provided for replacing parts in a vacuum chamber without venting the vacuum. A transfer system is used to transfer a removably mounted component from a processing module that is attached to a transfer system and replacing the component with another component from a maintenance system that is connected through an isolation assembly to a transfer module. The maintenance system may include a supply of replacement parts and receive expended or otherwise serviceable items that are to be replaced. These serviceable items may include chamber component that has a tendency to degrade during processes being performed in the processing module. Typically, such items are etched or eroded away or accumulate coatings, requiring occasional removal and replacement. Focus rings, chamber shields, dark space shields, insulators, deposition baffles and adaptors are some of the items requiring periodic replacement. Such items are installed in the process module in a way that permits their removal and replacement by a transfer arm or other transfer mechanism of the transfer system or otherwise by robotic mechanisms. The processing module may be an etching, deposition, ALD, patterning, developing, metrology, thermal processing, cleaning or other module used in a vacuum process, particularly for processing of semiconductor wafers.

Processing System And Method For Chemically Treating A Tera Layer

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US Patent:
20060006136, Jan 12, 2006
Filed:
Jul 6, 2004
Appl. No.:
10/883784
Inventors:
Aelan Mosden - Poughkeepsie NY, US
Asao Yamashita - Wappingers Falls NY, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
B44C 1/22
H01L 21/311
US Classification:
216037000, 216058000, 216067000, 438694000
Abstract:
A processing system and method for chemically treating a TERA layer on a substrate. The chemical treatment of the substrate chemically alters exposed surfaces on the substrate. In one embodiment, the system for processing a TERA layer includes a plasma-enhanced chemical vapor deposition (PECVD) system for depositing the TERA layer on the substrate, an etching system for creating features in the TERA layer, and a processing subsystem for reducing the size of the features in the TERA layer.

Processing System And Method For Chemically Treating A Tera Layer

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US Patent:
20060254716, Nov 16, 2006
Filed:
Jul 14, 2006
Appl. No.:
11/486105
Inventors:
Aelan Mosden - Poughkeepsie NY, US
Asao Yamashita - Wappingers Falls NY, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
C23F 1/00
H01L 21/306
C23C 16/00
US Classification:
156345430, 118715000
Abstract:
A processing system and method for chemically treating a TERA layer on a substrate. The chemical treatment of the substrate chemically alters exposed surfaces on the substrate. In one embodiment, the system for processing a TERA layer includes a plasma-enhanced chemical vapor deposition (PECVD) system for depositing the TERA layer on the substrate, an etching system for creating features in the TERA layer, and a processing subsystem for reducing the size of the features in the TERA layer.

Batch Processing System And Method For Performing Chemical Oxide Removal

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US Patent:
20070238301, Oct 11, 2007
Filed:
Mar 28, 2006
Appl. No.:
11/390470
Inventors:
Stephen Cabral - Pine Plains NY, US
Aelan Mosden - Poughkeepsie NY, US
Young Lee - Fishkill NY, US
International Classification:
H01L 21/461
H01L 21/302
US Classification:
438706000, 438714000, 438723000, 438743000
Abstract:
A batch processing system and method for chemical oxide removal (COR) is described. The batch processing system is configured to provide chemical treatment of a plurality of substrates, wherein each substrate is exposed to a gaseous chemistry, such as HF/NH, under controlled conditions including surface temperature and gas pressure. Furthermore, the batch processing system is configured to provide thermal treatment of a plurality of substrates, wherein each substrate is thermally treated to remove the chemically treated surfaces on each substrate.
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Aelan Mosden from Castleton on Hudson, NY, age ~52 Get Report