Adrian E Seigler

6738871, May 18, 2004

Dec 22, 2000

09/745830

Gary A. Van Huben - Poughkeepsie NY
Michael A. Blake - Wappingers Falls NY
Pak-Kin Mak - Poughkeepsie NY
Adrian Eric Seigler - Poughkeepsie NY

International Business Machines Corporation - Armonk NY

G06F 1200

711150, 711124, 711130, 711147, 711148

A remote resource management system for managing resources in a symmetrical multiprocessing environment having a plurality of clusters of symmetric multiprocessors each of which provides interfaces between cluster nodes of the symmetric multiprocessor system with a local interface and an interface controller. One or more remote storage controllers each has a local interface controller and a local-to-remote data bus. A remote fetch controller is responsible for processing data accesses in accordance with the methods described.

6738872, May 18, 2004

Dec 22, 2000

09/746686

Gary A. Van Huben - Poughkeepsie NY
Michael A. Blake - Wappingers Falls NY
Pak-Kin Mak - Poughkeepsie NY
Adrian Eric Seigler - Poughkeepsie NY

International Business Machines Corporation - Armonk NY

G06F 1200

711150, 711124, 711130, 711147, 711148

A remote resource management system for managing resources in a symmetrical multiprocessing environment having a plurality of clusters of symmetric multiprocessors each of which provides interfaces between cluster nodes of the symmetric multiprocessor system with a local interface and an interface controller. One or more remote storage controllers each has a local interface controller and a local-to-remote data bus. A remote fetch controller is responsible for processing data accesses across the clusters and a remote store controller is responsible for processing data accesses across the clusters. These controllers work in conjunction to provide a deadlock avoidance system for preventing hangs.

6988173, Jan 17, 2006

May 12, 2003

10/435878

Michael A. Blake - Wappingers Falls NY, US
Steven M. German - Wayland MA, US
Pak-kin Mak - Poughkeepsie NY, US
Adrian E. Seigler - Poughkeepsie NY, US
Gary A. Van Huben - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

G06F 12/00

711147

A bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. The bus protocol is used to exchange snoop requests and addresses, data, coherency information and operational status between nodes in a manner that allows partial coherency results to be passed in parallel with a snoop request and address as an operation is forwarded along each ring. Each node combines it's own coherency results with the partial coherency results it received prior to forwarding the snoop request, address and updated partial coherency results to the next node on the ring. The protocol allows each node in the system to see the final coherency results without requiring the requesting node to broadcast these results to all the other nodes in the system. The bus protocol also allows data to be returned on one of the two rings, with the ring selection determined by the relative placement of the source and destination nodes on each ring, in order to control latency and data bus utilization.

7085898, Aug 1, 2006

May 12, 2003

10/435776

Michael A. Blake - Wappingers Falls NY, US
Pak-kin Mak - Poughkeepsie NY, US
Adrian E. Seigler - Poughkeepsie NY, US
Gary A. VanHuben - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

G06F 12/00
G06F 15/167
H04L 12/43

711147, 711146, 711141, 711168, 370460

An apparatus and method is disclosed to manage storage coherency in a symmetric multiprocessing environment having a plurality of nodes, each of which contain a multitude of processors, I/O adapters, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. Local controllers on any given node initiate bus operations on behalf of said processors and I/O adapters on that node. Snoop requests are launched onto the ring topology simultaneously in both directions. As the messages traverse the nodes on the ring, they trigger remote controllers to perform coherent actions such as cache accesses or directory updates. Messages arriving on each node from both directions are combined with each other and with locally generated responses to form cumulative final responses. Additionally, controllers on the requesting node may perform local coherent actions based on the information conveyed by the returning final responses.

7111130, Sep 19, 2006

Apr 12, 2006

11/402599

Michael A. Blake - Wappingers Falls NY, US
Pak-kin Mak - Poughkeepsie NY, US
Adrian E. Seigler - Poughkeepsie NY, US
Gary A. VanHuben - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

G06F 12/00

711147

A shared memory symmetrical processing system including a plurality of nodes each having a system control element for routing internodal communications. A first ring and a second ring interconnect the plurality of nodes, wherein data in said first ring flows in opposite directions with respect to said second ring. A receiver receives a plurality of incoming messages via the first or second ring and merges a plurality of incoming message responses with a local outgoing message response to provide a merged response. Each of the plurality of nodes includes any combination of the following: at least one processor, cache memory, a plurality of I/O adapters, and main memory. The system control element includes a plurality of controllers for maintaining coherency in the system.

7448008, Nov 4, 2008

Aug 29, 2006

11/468078

Adrian E. Seigler - Poughkeepsie NY, US
Gary A. Van Huben - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

G06F 17/50
G06F 19/00

716 6, 703 16

Automated verification methodology parsing scripts auto generate testbench hardware design language, such as VHDL or Verilog, from the design source VHDL or Verilog. A formal verification model is then built comprising the testbench VHDL and the design under test. The resulting design verification tool then provides proofs and counterexamples for all of the rules, e. g. , auto-generated rules, in the testbench.

7661050, Feb 9, 2010

May 4, 2007

11/744392

Gary Van Huben - Poughkeepsie NY, US
Adrian E. Seigler - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

G01R 31/3187
G01R 31/40

714733, 714724

The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known practice in the chip design industry. Described herein is a method for verifying that any particular implementation of partial fencing logic actually provides the desired behavior of blocking down-stream impact of all signals from fenced interfaces, and also ensuring that the partial fencing does not inadvertently preclude any common logic from being fully tested.

7971166, Jun 28, 2011

Jun 15, 2008

12/139483

Adrian E. Seigler - Poughkeepsie NY, US
Gary A. Van Huben - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

G06F 17/50

716106, 716111, 716136, 703 16

Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.