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Adit Deva Singh

from Auburn, AL
Age ~69
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Also known as:
Adit D Singh, Deva Singh Adit, Devika Singh
Phone and address:
1979 Stoneridge Dr, Auburn, AL 36830
(334) 826-2260
Related to:
Ranjit K Singh, 63Chandrika R Singh, 66Deva Singh Eshan, 36Devika Singh, 35Alaka SinghHarmeet K Pabla, 51Eshan D Singh, 36
Connected to:
A Singh, 61Aakash Singh, 52Aaron A Singh, 36Abheyjot Singh, 50Abhijot Singh, 30Adarsh P Singh, 69Adrian A Singh, 46Agyapal Singh, 32Ajayvir Singh, 36Ajit Singh, 56

Adit Singh Phones & Addresses

  • 1979 Stoneridge Dr, Auburn, AL 36830 (334) 826-2260
  • 932 Parklane Rd, Auburn, AL 36830 (334) 482-2260
  • 1522 Benedict Pl, Auburn, AL 36832 (334) 826-2260
  • 459 Arnell Ln, Auburn, AL 36830 (334) 826-2260
  • 15 Hillside Ave, Princeton Township, NJ 08540 (609) 497-0754 (609) 497-4551
  • Princeton, NJ
  • Amherst, MA

Resumes

Resumes

Adit Singh Photo 1

Professor

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Location:
Auburn, AL
Industry:
Higher Education
Work:
Auburn University
Professor
Education:
Indian Institute of Technology, Kanpur
Adit Singh Photo 2

Professor At Auburn University

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Location:
Auburn, Alabama Area
Industry:
Higher Education

Publications

Isbn (Books And Publications)

Records of the 2003 IEEE International Workshop on Memory Technology, Design and Testing, 28-29 July, 2003, San Jose, California

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Author

Adit Singh

ISBN #

0769520049

Us Patents

System And Method For Estimating Reliability Of Components For Testing And Quality Optimization

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US Patent:
7409306, Aug 5, 2008
Filed:
Mar 6, 2007
Appl. No.:
11/715172
Inventors:
Adit D. Singh - Auburn AL, US
Thomas S. Barnett - South Burlington VT, US
Assignee:
Auburn University - Auburn AL
International Classification:
G06F 19/00
US Classification:
702 81, 702 35, 702 82, 702 83, 702 84, 700109, 700110, 700121
Abstract:
A system and method for determining the early life reliability of an electronic component, including classifying the electronic component based on an initial determination of a number of fatal defects, and estimating a probability of latent defects present in the electronic component based on that classification with the aim of optimizing test costs and product quality.

Systems And Methods For Providing Defect-Tolerant Logic Devices

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US Patent:
7696774, Apr 13, 2010
Filed:
May 20, 2008
Appl. No.:
12/123972
Inventors:
Adit D. Singh - Auburn AL, US
Abhijit Chatterjee - Marietta GA, US
International Classification:
H03K 19/003
US Classification:
326 13, 714724
Abstract:
The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.

System And Method For Estimating Reliability Of Components For Testing And Quality Optimization

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US Patent:
20030120457, Jun 26, 2003
Filed:
Oct 18, 2002
Appl. No.:
10/274439
Inventors:
Adit Singh - Auburn AL, US
Thomas Barnett - South Burlington VT, US
International Classification:
G06F015/00
US Classification:
702/181000
Abstract:
A system and method for determining the early life reliability of an electronic component, including classifying the electronic component based on an initial determination of a number of fatal defects, and estimating a probability of latent defects present in the electronic component based on that classification with the aim of optimizing test costs and product quality.

System And Method For Estimating Reliability Of Components For Testing And Quality Optimization

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US Patent:
20080281541, Nov 13, 2008
Filed:
Mar 31, 2008
Appl. No.:
12/080159
Inventors:
Adit D. Singh - Auburn AL, US
Thomas S. Barnett - South Burlington VT, US
International Classification:
G06F 19/00
US Classification:
702 81
Abstract:
A system and method for determining the early life reliability of an electronic component, including classifying the electronic component based on an initial determination of a number of fatal defects, and estimating a probability of latent defects present in the electronic component based on that classification with the aim of optimizing test costs and product quality.
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Adit Deva Singh from Auburn, AL, age ~69 Get Report