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Adil Bahadoor Phones & Addresses

  • Framingham, MA
  • Quincy, MA
  • Somerville, MA
  • Medford, MA
  • 100 Marina Dr APT 414, Quincy, MA 02171

Work

Company: Amd Jan 2013 Address: Boxborough MA Position: Member of technical staff

Education

Degree: MS School / High School: Tufts University 2003 to 2005 Specialities: Electrical Engineering

Skills

Static Timing Analysis • Rtl Design • Primetime • Physical Design • Vlsi • Timing Closure • Verilog • Application Specific Integrated Circuits • Mixed Signal • Asic • Low Power Design • Logic Design • Soc • Systemverilog • Perl • Integrated Circuit Design

Languages

English • French

Ranks

Certificate: Marketing Strategy Certificate

Industries

Higher Education

Resumes

Resumes

Adil Bahadoor Photo 1

Senior Manager R And D

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Location:
Quincy, MA
Industry:
Higher Education
Work:
AMD - Boxborough MA since Jan 2013
Member of Technical Staff

AMD - Boxborough MA Oct 2010 - Dec 2012
Sr. Design Engineer

Analog Devices - Norwood MA May 2005 - Oct 2010
Design Engineer
Education:
Tufts University 2003 - 2005
MS, Electrical Engineering
Tufts University 1999 - 2003
BS, Electrical Engineering
Skills:
Static Timing Analysis
Rtl Design
Primetime
Physical Design
Vlsi
Timing Closure
Verilog
Application Specific Integrated Circuits
Mixed Signal
Asic
Low Power Design
Logic Design
Soc
Systemverilog
Perl
Integrated Circuit Design
Languages:
English
French
Certifications:
Marketing Strategy Certificate

Publications

Us Patents

Methods And Apparatus For Performing Jump Operations In A Digital Processor

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US Patent:
20100146248, Jun 10, 2010
Filed:
Dec 4, 2008
Appl. No.:
12/328484
Inventors:
Christopher M. Mayer - Dover MA, US
Adil Bahadoor - Quincy MA, US
Michael Long - Arlington MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
G06F 9/30
G06F 9/38
US Classification:
712237, 712220, 712234, 712E09016, 712E09056, 712E09045
Abstract:
Methods and apparatus are provided for performing a jump operation in a pipelined digital processor. The method includes writing target addresses of jump instructions to be executed to a memory table, detecting a first jump instruction being executed by the processor, the first jump instruction referencing a pointer to a first target address in the memory table, the processor executing the first jump instruction by jumping to the first target address and modifying the pointer to point to a second target address in the memory table, the second target address corresponding to a second jump instruction. The execution of the first jump instruction may include prefetching at least one future target address from the memory table and writing the future target address in a local memory. The second target address may be accessed in the local memory in response to detection of the second jump instruction.
Adil N Bahadoor from Framingham, MA, age ~44 Get Report