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Adam Moerschell Phones & Addresses

  • Austin, TX
  • San Jose, CA
  • Sunnyvale, CA
  • Mountain View, CA
  • 2505 5Th St, Davis, CA 95616 (530) 750-2259
  • 651 Alvarado Ave, Davis, CA 95616
  • 565 Oxford Cir, Davis, CA 95616
  • Bend, OR

Public records

Vehicle Records

Adam Moerschell

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Address:
2880 Monroe Ter, San Jose, CA 95128
Phone:
(650) 969-6609
VIN:
JTMRK4DV1A5098071
Make:
TOYOTA
Model:
RAV4
Year:
2010

Resumes

Resumes

Adam Moerschell Photo 1

Asic Design Engineer

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Location:
San Francisco, CA
Industry:
Computer Hardware
Work:
Apple
Asic Design Engineer

Amd Oct 2006 - Sep 2012
Mts Asic Design Engineer

Amd Sep 2006 - Oct 2006
Asic Design Engineer

Uc Davis Sep 2005 - Sep 2006
Graduate Student Researcher

Los Alamos National Laboratory Jun 2005 - Sep 2005
Summer Intern
Education:
University of California, Davis 2004 - 2006
Master of Science, Masters, Computer Engineering
University of California, Davis 2000 - 2004
Bachelors, Bachelor of Science, Computer Engineering
Skills:
Asic
Computer Architecture
Soc
Verilog
Debugging
Rtl Design
Vlsi
Static Timing Analysis
Systemverilog
Semiconductors
Perl
Embedded Systems
Ic
Processors
Timing Closure
Adam Moerschell Photo 2

Adam Moerschell

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Publications

Us Patents

Level Of Detail Offset Determination

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US Patent:
20160364899, Dec 15, 2016
Filed:
Jun 10, 2015
Appl. No.:
14/735707
Inventors:
- Cupertino CA, US
Adam T. Moerschell - San Jose CA, US
Anthony P. DeLaurier - Los Altos CA, US
International Classification:
G06T 15/04
G06T 1/20
Abstract:
Techniques are disclosed relating to determining the location of a specified level of detail for a graphics texture. In some embodiments, an apparatus includes texture processing circuitry configured to receive information specifying a particular mipmap in a chain of stored mipmaps for a graphics texture and determine an offset address for the particular mipmap. In these embodiments, the texture processing circuitry is configured to determine the offset address by operating on a value that indicates a greatest potential chain size for chains of mipmaps in a graphics processing element. In these embodiments, the operating includes masking upper bits of the value based on a size of the texture and masking lower bits of the value based on a position of the specified mipmap in the chain of stored mipmaps. Disclosed techniques may reduce power consumption and/or area of circuitry configured to determine the offset.

Texture State Cache

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US Patent:
20160071232, Mar 10, 2016
Filed:
Sep 10, 2014
Appl. No.:
14/482828
Inventors:
- Cupertino CA, US
Adam T. Moerschell - San Jose CA, US
James S. Blomgren - Houston TX, US
International Classification:
G06T 1/60
G06T 1/20
G06T 7/00
G06T 7/40
G06T 11/00
Abstract:
Techniques are disclosed relating to a cache configured to store state information for texture mapping. In one embodiment, a texture state cache includes a plurality of entries configured to store state information relating to one or more stored textures. In this embodiment, the texture state cache also includes texture processing circuitry configured to retrieve state information for one of the stored textures from one of the entries in the texture state cache and determine pixel attributes based on the texture and the retrieved state information. The state information may include texture state information and sampler state information, in some embodiments. The texture state cache may allow for reduced rending times and power consumption, in some embodiments.
Adam T Moerschell from Austin, TX, age ~42 Get Report