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Adam C Malamy

from San Carlos, CA
Age ~62
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Related to:
Jason N Barcia, 49Allan R Malamy, 82Judith A Zimmerman, 82
Connected to:
Jonathan D Malamy, 53Ann M Malan, 78April L Malan, 44Bob D Malan, 71Cody S Malan, 35Connie Y Malan, 56Daniel S Malan, 48Jack L Malan, 75Jesse M Malan, 33Kathryn L Malan, 32

Adam Malamy Phones & Addresses

  • 33 Coronado Ave, San Carlos, CA 94070 (650) 224-8786
  • 3O Coronado Ave, San Carlos, CA 94070
  • 961 Pizarro Ln, San Mateo, CA 94404 (650) 574-3455
  • Foster City, CA
  • Fernley, NV
  • 500 Beale St, San Francisco, CA 94105
  • Boston, MA
  • Palo Alto, CA
  • Mountain View, CA
  • Redwood City, CA

Work

Company: Xilinx Jul 2019 Position: Director of engineering

Education

Degree: Master of Science, Masters, Bachelors, Bachelor of Science School / High School: Massachusetts Institute of Technology 1980 to 1987

Industries

Semiconductors

Resumes

Resumes

Adam Malamy Photo 1

Director Of Engineering

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Location:
33 Coronado Ave, San Carlos, CA 94070
Industry:
Semiconductors
Work:
Xilinx
Director of Engineering
Ngcodec Aug 2012 - Jul 2019
Founder and Vice President Technology
Cavium Inc Jan 2009 - Sep 2012
Director of Engineering, Verification
W&W Communications Apr 2006 - Dec 2008
Principle Engineer and Director Verification
Ubicom Jun 2002 - Mar 2006
Asic Design Verification Manager
Education:
Massachusetts Institute of Technology 1980 - 1987
Master of Science, Masters, Bachelors, Bachelor of Science

Publications

Us Patents

Identifying Silhouette Edges Of Objects To Apply Anti-Aliasing

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US Patent:
6529207, Mar 4, 2003
Filed:
May 31, 2000
Appl. No.:
09/584463
Inventors:
Edouard Landau - San Jose CA
Adrian Sfarti - Sunnyvale CA
Adam Malamy - Foster City CA
Mei-Chi Liu - Sunnyvale CA
Robert Laker - Fremont CA
Paolo Sabella - Pleasanton CA
Assignee:
WEBTV Networks, Inc. - Mountain View CA
International Classification:
G09A 500
US Classification:
345619, 345611
Abstract:
A graphics rendering system creates an image based on objects constructed of polygonal primitives, which can generate the perception of three-dimensional objects displayed on a two-dimensional display device. An anti-aliasing operation is applied to silhouette edges of the objects, which are the edges of primitives which are displayed at the perimeter of an object. A silhouette edge can be identified by determining how many times an edge is rendered, with each instance of the rendering of an edge corresponding to the rendering of a primitive that adjoins the edge. An edge that is rendered exactly once is interpreted as a silhouette edge. An example of a silhouette edge is an edge that adjoins one triangular primitive that is viewable and another triangular primitive that is hidden from view by other primitives. Another technique for identifying a silhouette edge can be applied to closed objects by determining whether a first primitive adjoining an edge is hidden from view by other primitives and a second primitive also adjoining the edge is viewable. Once the silhouette edges are identified, the anti-aliasing operation is applied thereto.

Modular Scaleable Processing Engine For Accelerating Variable Length Coding

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US Patent:
8013765, Sep 6, 2011
Filed:
May 1, 2008
Appl. No.:
12/150871
Inventors:
Adam Craig Malamy - San Carlos CA, US
Assignee:
Cavium, Inc. - San Jose CA
International Classification:
H03M 7/00
US Classification:
341107, 341 50
Abstract:
A mechanism for efficient CAVLC coding in a hardware implementation of a H. 264 coder is provided. In an embodiment of the present invention, multiple modular CAVLC engines that each process one sub-macroblock of data are used. An assembler engine that combines the CAVLC-encoded sub-macroblock data from each modular CAVLC engine to form a output bit-stream is also provided.

Polygon Rendering Method And System With Dedicated Setup Engine

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US Patent:
60942010, Jul 25, 2000
Filed:
Apr 8, 1998
Appl. No.:
9/057393
Inventors:
Adam Malamy - Foster City CA
Nicholas R. Baker - Cupertino CA
Robert Laker - Fremont CA
Padma Parthasarathy - Fremont CA
Adrian Sfarti - Sunnyvale CA
Assignee:
WebTV Networks, Inc. - Mountain View CA
International Classification:
G06T 1120
US Classification:
345441
Abstract:
A system and method of rendering polygons in graphics system using incremental iterative addition in place of complex division operations. A setup engine provides relevant values to edge and span walk modules for rapid processing and rendering of polygon characteristics including material values. Characteristic functions are iterated with respect to polygon area and along individual spans to derive values for each pixel therein.

Cache Memory System With Independently Accessible Subdivided Cache Tag Arrays

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US Patent:
56757654, Oct 7, 1997
Filed:
Feb 21, 1996
Appl. No.:
8/604687
Inventors:
Adam Malamy - Winchester MA
Rajiv N. Patel - San Jose CA
Norman M. Hayes - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
G06F 1208
G06F 1316
US Classification:
395473
Abstract:
Two independently accessible subdivided cache tag arrays and a cache control logic is provided to a set associative cache system. Each tag entry is stored in two subdivided cache tag arrays, a physical and a set tag array such that each physical tag array entry has a corresponding set tag array entry. Each physical tag array entry stores the tag addresses and control bits for a set of cache lines. The control bits comprise at least one validity bit indicating whether the data stored in the corresponding cache line is valid. Each set tag array entry stores the descriptive bits for a set of cache lines which consists of the most recently used (MRU) field identifying the most recently used cache lines of the cache set. Each subdivided tag array is provided with its own interface to enable each array to be accessed concurrently but independently by the cache control logic which performs read and write operations against the cache. The cache control logic makes concurrent and independent accesses to the separate tag arrays to read and write the control and descriptive information in the tag entries.

Cache Miss Buffer Adapted To Satisfy Read Requests To Portions Of A Cache Fill In Progress Without Waiting For The Cache Fill To Complete

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US Patent:
53534263, Oct 4, 1994
Filed:
Apr 29, 1992
Appl. No.:
7/875983
Inventors:
Rajiv N. Patel - San Jose CA
Adam Malamy - Winchester MA
Norman M. Hayes - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
G06F 1300
US Classification:
395425
Abstract:
A cache array, a cache tag and comparator unit and a cache multiplexor are provided to a cache memory. Each cache operation performed against the cache array, read or write, takes only half a clock cycle. The cache tag and comparator unit comprises a cache tag array, a cache miss buffer and control logic. Each cache operation performed against the cache tag array, read or write, also takes only half a clock cycle. The cache miss buffer comprises cache miss descriptive information identifying the current state of a cache fill in progress. The control logic comprises a plurality of combinatorial logics for performing tag match operations. In addition to standard tag match operations, the control logic also conditionally tag matches an accessing address against an address tag stored in the cache miss buffer. Depending on the results of the tag match operations, and further depending on the state of the current cache fill if the accessing address is part of the memory block frame of the current cache fill, the control logic provides appropriate signals to the cache array, the cache multiplexor, the main memory and the instruction/data destination. As a result, subsequent instruction/data requests that are part of a current cache fill in progress can be satisfied without having to wait for the completion of the current cache fill, thereby further reducing cache miss penalties and function unit idle time.

System And Method For Adjusting Pixel Parameters By Subpixel Positioning

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US Patent:
62190709, Apr 17, 2001
Filed:
Sep 30, 1998
Appl. No.:
9/164003
Inventors:
Nick Baker - Cupertino CA
Adam Malamy - Foster City CA
Adrian Sfarti - Sunnyvale CA
Paul Paternoster - Los Altos CA
Padma Parthasarathy - Fremont CA
Assignee:
WebTV Networks, Inc. - Mountain View CA
International Classification:
G06T 1570
US Classification:
345475
Abstract:
A method and system for simulating motion of a polygon on a display screen. The polygon may be included in a set of polygons used to model a three-dimensional object. The position of the polygon is defined by vertices tracked in a subpixel coordinate system existing in a computer-readable medium. The subpixel coordinates of the vertices are used to identify the pixels on the display screen having coordinates that correspond to subpixel coordinates lying within or, optionally, at the boundary of the polygon. The identified pixels are those that are to be lighted on the display screen to generate the image of the polygon. The display properties of the lighted pixels are selected by interpolation based on defined pixel display parameters assigned to the vertices of the triangle. As motion of the polygon is tracked in the subpixel coordinate system, the corresponding display on the display screen is repeatedly adjusted. The method of identifying and interpolating the display parameters of the pixels using the subpixel coordinate system provides the appearance of smooth polygon motion.

Controlling A Real-Time Rendering Engine Using A List-Based Control Mechanism

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US Patent:
57987629, Aug 25, 1998
Filed:
May 10, 1995
Appl. No.:
8/438860
Inventors:
Adrian Sfarti - Sunnyvale CA
Nicholas Robert Baker - Sunnyvale CA
Robert William Laker - Fremont CA
Adam Craig Malamy - Palo Alto CA
Assignee:
Cagent Technologies, Inc. - Redwood City CA
International Classification:
G06T 1500
US Classification:
345420
Abstract:
A system and method for controlling a real-time rendering engine includes a control program for defining in regions of system memory a block header and a list of flow-control instructions.

Method And Apparatus For Testing Cache Ram Residing On A Microprocessor

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US Patent:
57817219, Jul 14, 1998
Filed:
Sep 16, 1996
Appl. No.:
8/714515
Inventors:
Norman M. Hayes - Sunnyvale CA
Adam Malamy - Winchester MA
Rajiv N. Patel - San Jose CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
G11C 2900
US Classification:
39518318
Abstract:
An apparatus and method for enabling a cache controller and address and data buses of a microprocessor with an on-board cache to provide a SRAM test mode for testing the on-board cache. Upon assertion of a SRAM test signal to a SRAM test pin on the microprocessor chip, the cache and bus controllers cease normal functionality and permit data to be written to, and read from, individual addresses within the on-board cache as though the on-board cache is simple SRAM. After the chip is reset, standard SRAM tests can then be implemented by reading and writing data to selected cache memory addresses as though the cache memory were SRAM. Upon completion of the tests, the SRAM test signal is deasserted and the cache and bus controllers resume normal operating functionality. A reset signal is then applied to the microprocessor to reinitialize control logic employed within the microprocessor. In this way, cache memory on-board a microprocessor can be tested using standard SRAM testing algorithms and equipment thereby eliminating a need for specialized test equipment to test cache memory contained on a microprocessor chip.
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Adam C Malamy from San Carlos, CA, age ~62 Get Report