Search

Abram M Detofsky

from Portland, OR
Age ~51
Get Report
Also known as:
Detofsky Abram, Abram Y
Phone and address:
12930 SW 113Th Pl, Portland, OR 97223
Related to:
Sandy M Barnes, 47Lisa M James, 44Brian James, 47James JamesJacqueline James, 91
Connected to:
Philip L Detol, 56Roni Detoledo, 70Anthony Detomasso, 70Nicholas J Detomaso, 45John P Detombe, 53Michele S Detombeur, 50Denise K Detommaso, 66Keith E Detommaso, 62George J Detorakis, 60Anthony M Detore, 46

Abram Detofsky Phones & Addresses

  • 12930 SW 113Th Pl, Portland, OR 97223
  • 7604 Insley St, Portland, OR 97206
  • Tigard, OR
  • 6937 Ronler Way, Hillsboro, OR 97124 (503) 640-3093
  • 3055 Tyndall Ave, Tucson, AZ 85719 (520) 670-9624
  • Willingboro, NJ
  • Orangevale, CA

Work

Company: Intel corporation Aug 1999 Position: Senior manufacturing test research and development engineer

Education

School / High School: University of Arizona 1997 to 1999

Skills

Semiconductors • Dft

Interests

Entertaining • Cooking • High Powered Model Rocketry • Hiking • Biking

Emails

a***[email protected]

Industries

Semiconductors

Resumes

Resumes

Abram Detofsky Photo 1

Senior Manufacturing Test Research And Development Engineer

View page
Location:
Portland, OR
Industry:
Semiconductors
Work:
Intel Corporation
Senior Manufacturing Test Research and Development Engineer
Education:
University of Arizona 1997 - 1999
Rochester Institute of Technology 1992 - 1997
Bachelors, Bachelor of Science, Engineering
Skills:
Semiconductors
Dft
Interests:
Entertaining
Cooking
High Powered Model Rocketry
Hiking
Biking

Business Records

Name / Title
Company / Classification
Phones & Addresses
Abram Detofsky
Principal
Compasspoint Software Studios, LLC
Misc Personal Services
12930 SW 113 Pl, Portland, OR 97223

Publications

Us Patents

Mapping Variations In Local Temperature And Local Power Supply Voltage That Are Present During Operation Of An Integrated Circuit

View page
US Patent:
7233163, Jun 19, 2007
Filed:
Apr 18, 2006
Appl. No.:
11/405882
Inventors:
Arun Krishnamoorthy - Portland OR, US
Abram M. Detofsky - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G01R 31/26
US Classification:
324765, 324763, 702132
Abstract:
A method includes providing an integrated circuit (IC) having a plurality of oscillators at distributed locations in the IC, determining a respective rate of oscillation of each of the oscillators, and detecting variations in local temperature in the IC based on the determined rates of oscillation. Other embodiments are described and claimed.

Mapping Variations In Local Temperature And Local Power Supply Voltage That Are Present During Operation Of An Integrated Circuit

View page
US Patent:
20050258838, Nov 24, 2005
Filed:
May 21, 2004
Appl. No.:
10/851631
Inventors:
Arun Krishnamoorthy - Portland OR, US
Abram Detofsky - Portland OR, US
International Classification:
G01R035/00
US Classification:
324601000
Abstract:
A method includes providing an integrated circuit (IC) having a plurality of oscillators at distributed locations in the IC, determining a respective rate of oscillation of each of the oscillators, and detecting variations in local temperature in the IC based on the determined rates of oscillation. Other embodiments are described and claimed.

Micro Positioning Test Socket And Methods For Active Precision Alignment And Co-Planarity Feedback

View page
US Patent:
20120074975, Mar 29, 2012
Filed:
Sep 23, 2010
Appl. No.:
12/888579
Inventors:
Abram M. Detofsky - Tigard OR, US
Todd P. Albertson - Warren OR, US
David Shia - Hillsboro OR, US
International Classification:
G01R 31/28
G01B 11/14
H01R 13/64
US Classification:
32475017, 439374, 356614
Abstract:
Methods and structures for testing a microelectronic packaging structure/device are described. Those methods may include placing a device in a floating carrier, wherein the floating carrier is coupled to a socket housing by pin dowels disposed in four corners of the socket housing, and wherein at least two actuating motors are disposed within the socket housing, and micro adjusting the device by utilizing a capacitive coupled or a fiber optic alignment system wherein a maximum measured capacitance or maximum measured intensity between alignment structures disposed in the socket housing and alignment package balls disposed within the device indicate optimal alignment of the device. Methods further include methods for active co-planarity detection through the use of a capacitive-coupled techniques.

Integrated Circuit Test Temperature Control Mechanism

View page
US Patent:
20140062513, Mar 6, 2014
Filed:
Aug 31, 2012
Appl. No.:
13/600486
Inventors:
John C. Johnson - Phoenix AZ, US
James G. Maveety - Campbell CA, US
Abram M. Detofsky - Tigard OR, US
James E. Neeb - Gilbert AZ, US
International Classification:
G01R 1/44
H05K 7/20
US Classification:
32475003, 236 1 F
Abstract:
A thermal controller includes a thermal control interface to receive test data from an automated test equipment (ATE) system and dynamically adjust a target setpoint temperature based on the data and a dynamic thermal controller to receive the target setpoint temperature from the thermal control interface and control a thermal actuator based on the target setpoint temperature.

Stackable Photonics Die With Direct Optical Interconnect

View page
US Patent:
20220196915, Jun 23, 2022
Filed:
Dec 23, 2020
Appl. No.:
17/132912
Inventors:
- Santa Clara CA, US
Michael RUTIGLIANO - Hillsboro OR, US
Joe F. WALCZYK - Tigard OR, US
Abram M. DETOFSKY - Tigard OR, US
International Classification:
G02B 6/12
H01L 33/62
H01L 33/58
H04B 10/40
H01L 25/075
Abstract:
Embodiments described herein may be related to apparatuses, processes, and techniques related to incorporating photonics integrated circuitry into a base die, the base die including an optical interconnect at a bottom of the base die to transmit and to receive light signals from outside the base die. The top of the base die includes one or more electrical connectors that are electrically coupled with the photonics integrated circuitry. The base die may be referred to as the photonics die. A system-on-a-chip (SOC) may be electrically coupled with and stacked onto the top of the photonics die. Other embodiments may be described and/or claimed.

Pierceable Protective Cover For Photonic Connectors

View page
US Patent:
20220196924, Jun 23, 2022
Filed:
Dec 22, 2020
Appl. No.:
17/131630
Inventors:
- Santa Clara CA, US
Todd R. COONS - Gilbert AZ, US
Michael RUTIGLIANO - Chandler AZ, US
Abram M. DETOFSKY - Tigard OR, US
International Classification:
G02B 6/38
Abstract:
A photonic connector comprises a first ferrule having a first plurality of optical fibers. A membrane cover is attached to the first ferrule and covers ends of the first plurality of optical fibers. Once the first ferrule is mated with a second ferrule having a second plurality of optical fibers, the membrane cover is pierced by the first plurality of optical fibers, the second plurality of optical fibers, or both.

Stacked Instrument Architecture For Testing And Validation Of Electronic Circuits

View page
US Patent:
20190293707, Sep 26, 2019
Filed:
Nov 28, 2017
Appl. No.:
16/339834
Inventors:
- Santa Clara CA, US
Abram M. DETOFSKY - Tigard OR, US
Jin PAN - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G01R 31/28
Abstract:
In one embodiment, a device to test one or more electronic components comprises a first card comprising a first test device communicatively coupled to at least a first connector assembly positioned on the first card and a second card comprising a second test device communicatively coupled to at least a second connector assembly positioned on the second card. The at least a first connector assembly is directly communicatively coupled to the at least a second connector assembly to provide a direct communication interface between the first test device and the second test device that is not routed via a backplane. Other embodiments may be described.

Stacked Instrument Architecture For Testing And Validation Of Electronic Circuits

View page
US Patent:
20180188288, Jul 5, 2018
Filed:
Dec 29, 2016
Appl. No.:
15/393640
Inventors:
- Santa Clara CA, US
Abram M. Detofsky - Tigard OR, US
Jin Pan - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G01R 1/04
G01R 31/28
Abstract:
In one embodiment, a device to test one or more electronic components comprises a first card comprising a first test device communicatively coupled to at least a first connector assembly positioned on the first card and a second card comprising a second test device communicatively coupled to at least a second connector assembly positioned on the second card. The at least a first connector assembly is directly communicatively coupled to the at least a second connector assembly to provide a direct communication interface between the first test device and the second test device that is not routed via a backplane. Other embodiments may be described.
Control profile
Abram M Detofsky from Portland, OR, age ~51 Get Report