Abner F Bello

20140017903, Jan 16, 2014

Jul 10, 2012

13/545646

Abner Bello - Troy NY, US
Abhijeet Paul - Albany NY, US

GLOBALFOUNDRIES INC. - Grand Cayman

H01L 21/304
H01L 21/31

438758, 438800, 257E21237, 257E2124

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a first surface. In the method, a stress is applied to the semiconductor substrate to change inter-atomic spacing at the first surface of the semiconductor substrate to a stressed inter-atomic spacing. Then, the semiconductor substrate is processed. Thereafter, the stress is released and the first surface of the processed semiconductor substrate retains the stressed inter-atomic spacing.

20120144642, Jun 14, 2012

Dec 10, 2010

12/965769

Robert Steinkraus - San Francisco CA, US
Abner F. Bello - Pleasanton CA, US

G01N 29/04
G01N 29/00

2940701, 73579

A method and apparatus for film thickness measurements by inducing and detecting acoustic resonance in a sample is disclosed. Acoustic resonance is induced by generating acoustic waves using heterodyned laser beams to frequency-tune a periodic waveform; the detection is done by monitoring changes in a continuous wave, constant intensity laser probe beam. The laser beams and optical system are fiber-optic based.

20160190306, Jun 30, 2016

Mar 8, 2016

15/063633

- Grand Cayman, KY
Vimal K. Kamineni - Albany NY, US
Abner F. Bello - Clifton Park NY, US
Nicholas V. LiCausi - Watervliet NY, US
Wenhui Wang - Clifton Park NY, US
Michael Wedlake - Albany NY, US
Jason R. Cantone - Mechanicville NY, US

H01L 29/78
H01L 29/10
H01L 29/51
H01L 29/06

One illustrative device disclosed herein includes, among other things, a semiconductor substrate, a fin structure, a gate structure positioned around a portion of the fin structure in the channel region of the device, spaced-apart portions of a second semiconductor material positioned vertically between the fin structure and the substrate, wherein the second semiconductor material is a different semiconductor material than that of the fin, and a local channel isolation material positioned laterally between the spaced-apart portions of the second semiconductor material and vertically below the fin structure and the gate structure, wherein the local channel isolation material is positioned under at least a portion of the channel region of the device.

20150294912, Oct 15, 2015

May 29, 2015

14/725663

- Grand Cayman, KY
Vimal K. Kamineni - Albany NY, US
Abner F. Bello - Clifton Park NY, US
Nicholas V. LiCausi - Watervliet NY, US
Wenhui Wang - Clifton Park NY, US
Michael Wedlake - Albany NY, US
Jason R. Cantone - Mechanicville NY, US

H01L 21/8234
H01L 21/308
H01L 29/78
H01L 21/3213
H01L 21/02
H01L 29/66
H01L 21/762

One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

20150198435, Jul 16, 2015

Jan 15, 2014

14/155504

- Grand Cayman, KY
Abner BELLO - Clifton Park NY, US
Sipeng GU - Clifton Park NY, US
Lokesh SUBRAMANY - Clifton Park NY, US
Xiang HU - Clifton Park NY, US
Akshey SEHGAL - Malta NY, US

GLOBALFOUNDRIES Inc. - Grand Cayman

G01B 11/06
H01L 21/66

Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.

20150129934, May 14, 2015

Nov 13, 2013

14/079159

- Grand Cayman, KY
Vimal K. Kamineni - Albany NY, US
Abner F. Bello - Clifton Park NY, US
Nicholas V. LiCausi - Watervliet NY, US
Wenhui Wang - Clifton Park NY, US
Michael Wedlake - Albany NY, US
Jason R. Cantone - Mechanicville NY, US

GLOBALFOUNDRIES Inc. - Grand Cayman

H01L 27/088
H01L 29/06
H01L 29/165
H01L 21/8234

257192, 438283

One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

20150041906, Feb 12, 2015

Aug 6, 2013

13/960200

- Grand Cayman, KY
Derya Deniz - Troy NY, US
Abner Bello - Clifton Park NY, US
Abhijeet Paul - Albany NY, US
Robert J. Miller - Yorktown Heights NY, US

GLOBALFOUNDRIES Inc. - Grand Cayman

H01L 21/8238
H01L 27/092

257369, 438199

One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

20140319614, Oct 30, 2014

Apr 25, 2013

13/870854

- Grand Cayman, KY
Abner BELLO - Clifton Park NY, US
Vimal K. KAMINENI - Albany NY, US
Derya DENIZ - Troy NY, US

GLOBALFOUNDRIES, Inc. - Grand Cayman

H01L 29/66
H01L 29/78

257365, 438283

Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.