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Abdulla M Bataineh

from Eau Claire, WI
Age ~61
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Also known as:
Moh Bataineh Abdulla, Abdulla M Bathine, Bataineh Abdulla, Abdulla H
Phone and address:
3815 Southwind Dr, Eau Claire, WI 54701
(715) 552-1877
Related to:
Mariamkh BatainehAhnaf Bataineh, 56Charlotte Lang, 58Ahnaf Bataineh
Connected to:
Mahmoud Bataineh, 62Muna F Bataineh, 43Adil Batal, 41Laurie Batal, 59Sami K Batal, 62Tarik Batal, 38Catarina Batalau, 29Daryl Batalden, 80Hedviga Batalden, 49Matthew J Batalden, 53

Abdulla Bataineh Phones & Addresses

  • 3815 Southwind Dr, Eau Claire, WI 54701 (715) 552-1877
  • 3727 Valley View Dr, Eau Claire, WI 54701 (715) 835-5003 (715) 833-2007
  • 2701 Ellis St, Eau Claire, WI 54701 (715) 552-1877
  • 1993 Wellington Ln APT 92, Vista, CA 92081 (760) 216-1945
  • 2999 Hamilton Ave, Altoona, WI 54720 (715) 552-1877
  • Saint Paul, MN
  • Minneapolis, MN

Work

Company: Cray inc. Position: Architect

Education

School / High School: The Ohio State University 1987 to 1991

Industries

Computer Hardware

Resumes

Resumes

Abdulla Bataineh Photo 1

Architect

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Location:
Eau Claire, WI
Industry:
Computer Hardware
Work:
Cray Inc.
Architect
Education:
The Ohio State University 1987 - 1991

Publications

Us Patents

Optimized High Bandwidth Cache Coherence Mechanism

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US Patent:
7082500, Jul 25, 2006
Filed:
Feb 18, 2003
Appl. No.:
10/368090
Inventors:
Steven L. Scott - Eau Claire WI, US
Abdulla Bataineh - Eau Claire WI, US
Assignee:
Cray, Inc. - Chippewa Falls WI
International Classification:
G06F 12/00
US Classification:
711141, 711142, 711143, 711144
Abstract:
A method and apparatus for a coherence mechanism that supports a distributed memory programming model in which processors each maintain their own memory area, and communicate data between them. A hierarchical programming model is supported, which uses distributed memory semantics on top of shared memory nodes. Coherence is maintained globally, but caching is restricted to a local region of the machine (a “node” or “caching domain”). A directory cache is held in an on-chip cache and is multi-banked, allowing very high transaction throughput. Directory associativity allows the directory cache to map contents of all caches concurrently. References off node are converted to non-allocating references, allowing the same access mechanism (a regular load or store) to be used for both for intra-node and extra-node references. Stores (Puts) to remote caches automatically update the caches instead of invalidating the caches, allowing producer/consumer data sharing to occur through cache instead of through main memory.

Optimized High Bandwidth Cache Coherence Mechanism

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US Patent:
7409505, Aug 5, 2008
Filed:
Jul 11, 2006
Appl. No.:
11/456781
Inventors:
Steven L. Scott - Eau Claire WI, US
Abdulla Bataineh - Eau Claire WI, US
Assignee:
Cray, Inc. - Seattle WA
International Classification:
G06F 12/00
US Classification:
711141, 711147
Abstract:
A method and apparatus for a coherence mechanism that supports a distributed memory programming model in which processors each maintain their own memory area, and communicate data between them. A hierarchical programming model is supported, which uses distributed memory semantics on top of shared memory nodes. Coherence is maintained globally, but caching is restricted to a local region of the machine (a “node” or “caching domain”). A directory cache is held in an on-chip cache and is multi-banked, allowing very high transaction throughput. Directory associativity allows the directory cache to map contents of all caches concurrently. References off node are converted to non-allocating references, allowing the same access mechanism (a regular load or store) to be used for both for intra-node and extra-node references. Stores (Puts) to remote caches automatically update the caches instead of invalidating the caches, allowing producer/consumer data sharing to occur through cache instead of through main memory.

Configurable Vector Length Computer Processor

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US Patent:
8601236, Dec 3, 2013
Filed:
Feb 29, 2012
Appl. No.:
13/409033
Inventors:
Gregory J. Faanes - Chippewa Falls WI, US
Eric P. Lundberg - Chippewa Falls WI, US
Abdulla Bataineh - Chippewa Falls WI, US
Timothy J. Johnson - Chippewa Falls WI, US
Michael Parker - Chippewa Falls WI, US
James Robert Kohn - St. Paul MN, US
Steven L. Scott - Chippewa Falls WI, US
Robert Alverson - Seattle WA, US
Assignee:
Cray Inc. - Seattle WA
International Classification:
G06F 15/00
US Classification:
712 7
Abstract:
A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.

Configurable Vector Length Computer Processor

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US Patent:
20100115234, May 6, 2010
Filed:
Oct 31, 2008
Appl. No.:
12/263302
Inventors:
Gregory J. Faanes - Chippewa Falls WI, US
Eric P. Lundberg - Chippewa Falls WI, US
Abdulla Bataineh - Chippewa Falls WI, US
Timothy J. Johnson - Chippewa Falls WI, US
Michael Parker - Chippewa Falls WI, US
James Robert Kohn - Mendota Heights MN, US
Steven L. Scott - Chippewa Falls WI, US
Robert Alverson - Seattle WA, US
Assignee:
CRAY INC. - SEATTLE WA
International Classification:
G06F 15/76
G06F 9/06
US Classification:
712 7, 712E09003
Abstract:
A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.

Hierarchical Shared Semaphore Registers

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US Patent:
20100115236, May 6, 2010
Filed:
Oct 31, 2008
Appl. No.:
12/263305
Inventors:
Abdulla Bataineh - Chippewa Falls WI, US
James Robert Kohn - Mendota Heights MN, US
Eric P. Lundberg - Chippewa Fall WI, US
Timothy J. Johnson - Chippewa Falls WI, US
Thomas L. Court - Chippewa Falls WI, US
Gregory J. Faanes - Chippewa Falls WI, US
Steven L. Scott - Chippewa Falls WI, US
Assignee:
Cray inc. - seattle WA
International Classification:
G06F 15/76
G06F 9/06
US Classification:
712 29, 712E09003
Abstract:
A multiprocessor computer system having a plurality of processing elements comprises one or more core-level hierarchical shared semaphore registers, wherein each core-level hierarchical shared semaphore register is coupled to a different processor core. Each hierarchical shared semaphore register is writable to each of a plurality of streams executing on the coupled processor core. One or more chip-level hierarchical shared semaphore registers are also coupled to plurality of processor cores, each chip-level hierarchical shared semaphore register writable to each of the plurality of processor cores.

Multiprocessor Computer Cache Coherence Protocol

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US Patent:
20100318741, Dec 16, 2010
Filed:
Jun 12, 2009
Appl. No.:
12/483915
Inventors:
Steven L. Scott - Chippewa Falls WI, US
Gregory J. Faanes - Chippewa Falls WI, US
Abdulla Bataineh - Eau Claire WI, US
Michael Bye - Chippewa Falls WI, US
Gerald A. Schwoerer - Chippewa Falls WI, US
Dennis C. Abts - Eleva WI, US
Assignee:
Cray Inc. - Seattle WA
International Classification:
G06F 12/08
G06F 12/00
US Classification:
711122, 711141, 711E12001, 711E12026
Abstract:
A multiprocessor computer system comprises a processing node having a plurality of processors and a local memory shared among processors in the node. An L data cache is local to each of the plurality of processors, and an L cache is local to each of the plurality of processors. An L cache is local the node but shared among the plurality of processors, and the L cache is a subset of data stored in the local memory. The L caches are subsets of the L cache, and the L caches are a subset of the L caches in the respective processors.

Efficient Memory Structure Simulation For Sequential Circuit Design Verification

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US Patent:
6813599, Nov 2, 2004
Filed:
Jul 17, 2000
Appl. No.:
09/617367
Inventors:
Thomas Court - Eau Claire WI
Abdulla Bataineh - Eau Claire WI
Dennis Kuba - Chippewa Falls WI
Assignee:
Silicon Graphics, Inc. - Mountain View CA
International Classification:
G06F 1750
US Classification:
703 14, 703 20
Abstract:
A method for efficiently simulating memory structures of a sequential circuit for design verification of the sequential circuit. The method is implemented by an computer system having a processor coupled to a memory via a bus, the memory storing computer readable code which when executed by the processor cause the computer system to perform the steps of the memory structure simulation method. The method includes accessing a netlist description of a sequential circuit, wherein the description is for realizing the sequential circuit in a physical form. Memory elements included within the description are identified. For these memory elements, inputs to the memory elements and outputs from the memory elements are identified. Using this information, the memory elements are grouped into at least one group of functionally related memory elements. Subsequently, the memory elements of the one or more groups are collectively addressed as a group.

System And Method For Facilitating Data-Driven Intelligent Network With Ingress Port Injection Limits

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US Patent:
20220353199, Nov 3, 2022
Filed:
Mar 23, 2020
Appl. No.:
17/594778
Inventors:
- Houston TX, US
Abdulla Bataineh - Vista CA, US
Thomas Court - Three Lakes WI, US
Jonathan P. Beecroft - Bristol Somerset, GB
International Classification:
H04L 47/6275
H04L 47/2466
H04L 47/2483
H04L 47/2441
H04L 47/625
Abstract:
Data-driven intelligent networking systems and methods are provided. The system can accommodate dynamic traffic while applying injection limits to different traffic classes at an ingress edge port. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow can be acknowledged after reaching the egress point of the network, and the acknowledgement packets can be sent back to the ingress point of the flow along the same data path. Furthermore, an edge switch can dynamically allocate the ingress port bandwidth among the traffic classes that are active at a given moment.
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Abdulla M Bataineh from Eau Claire, WI, age ~61 Get Report