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Abdalla A Naem

from San Jose, CA
Age ~73
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Also known as:
Adella A Naem
Phone and address:
820 Saratoga Ave, San Jose, CA 95129
(408) 564-6481
Related to:
Sanaa Naem
Connected to:
Onta S Naenphan, 46Lincoln K Naeole, 51Christine Naerbo, 70Linda A Naerheim, 51Deborah S Naert, 77Jessica N Naert, 35Roch A Naert, 39Stephen R Naert, 71Austin Naes, 36Christian A Naes, 30

Abdalla Naem Phones & Addresses

  • 820 Saratoga Ave, San Jose, CA 95129 (408) 564-6481
  • Sunnyvale, CA
  • Santa Clara, CA
  • Saratoga, CA

Publications

Us Patents

Copper-Topped Interconnect Structure That Has Thin And Thick Copper Traces And Method Of Forming The Copper-Topped Interconnect Structure

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US Patent:
7709956, May 4, 2010
Filed:
Sep 15, 2008
Appl. No.:
12/283852
Inventors:
Abdalla Aly Naem - San Jose CA, US
Reda Razouk - Sunnyvale CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 23/48
H01L 23/52
H01L 29/40
H01L 23/053
H01L 23/12
H01L 27/10
H01L 29/74
US Classification:
257758, 257211, 257700, 257759, 257760, 257E21575, 257E21627, 257E21641, 257762
Abstract:
A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide copper traces, on the same chip.

Stacked Die Structure With An Underlying Copper-Topped Die

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US Patent:
7847385, Dec 7, 2010
Filed:
Aug 24, 2007
Appl. No.:
11/895334
Inventors:
Abdalla Aly Naem - San Jose CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 23/02
US Classification:
257686, 257E23027
Abstract:
A copper-topped die, which has exposed copper lines and pads, is utilized as the lower die in a stacked die structure. A non-conductive material is formed over the lower copper-topped die, and then selectively removed so that the non-conductive material covers and lies between the copper lines while none of the non-conductive material lies over the copper pads. An upper die is then attached to the non-conductive material.

Fuse Target And Method Of Forming The Fuse Target In A Copper Process Flow

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US Patent:
7964934, Jun 21, 2011
Filed:
May 22, 2007
Appl. No.:
11/805054
Inventors:
Abdalla Aly Naem - San Jose CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 23/52
US Classification:
257529, 257E23149
Abstract:
A fuse target is fabricated in a copper process by forming a number of copper targets at the same time that the copper traces are formed. After the copper targets and the copper traces have been formed, metal targets, such as aluminum targets, are formed on the copper targets at the same time that metal bonding pads, such as aluminum bonding pads, are formed on the copper traces.

Copper-Compatible Fuse Target

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US Patent:
8030733, Oct 4, 2011
Filed:
May 22, 2007
Appl. No.:
11/805056
Inventors:
Abdalla Aly Naem - San Jose CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 23/62
US Classification:
257529, 257209, 257729, 257E23149, 257E21592, 438128, 438129
Abstract:
A copper-compatible fuse target is fabricated by forming a copper target structure at the same time that the copper traces are formed. After the copper target structure and the copper traces have been formed, a conductive target, such as an aluminum target, is formed on the copper target structure at the same time that conductive connection portions, such as aluminum pads, are formed on the copper traces. A trench is then etched around the copper target structure and conductive target to form a fuse target.

Method Of Forming A Copper-Compatible Fuse Target

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US Patent:
8273608, Sep 25, 2012
Filed:
Sep 8, 2011
Appl. No.:
13/228297
Inventors:
Abdalla Aly Naem - San Jose CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 23/62
US Classification:
438132, 438215, 438281
Abstract:
A copper-compatible fuse target is fabricated by forming a target structure at the same time that a trace structure is formed on a passivation layer, followed by the formation of an overlying non-conductive structure. After the overlying non-conductive structure has been formed, a passivation opening is formed in the non-conductive structure to expose the passivation layer and the side wall of the target structure.

Growth Of Group Iii Nitride-Based Structures And Integration With Conventional Cmos Processing Tools

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US Patent:
8318563, Nov 27, 2012
Filed:
May 19, 2010
Appl. No.:
12/800606
Inventors:
Sandeep R. Bahl - Palo Alto CA, US
Abdalla Naem - San Jose CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21/336
US Classification:
438285, 257192, 257E21441
Abstract:
A method includes forming a non-continuous epitaxial layer over a semiconductor substrate. The substrate includes multiple mesas separated by trenches. The epitaxial layer includes crystalline Group III nitride portions over at least the mesas of the substrate. The method also includes depositing a dielectric material in the trenches. The method could also include forming spacers on sidewalls of the mesas and trenches or forming a mask over the substrate that is open at tops of the mesas. The epitaxial layer could also include Group III nitride portions at bottoms of the trenches. The method could further include forming gate structures, source and drain contacts, conductive interconnects, and conductive plugs over at least one crystalline Group III nitride portion, where at least some interconnects and plugs are at least partially over the trenches. The gate structures, source and drain contacts, interconnects, and plugs could be formed using standard silicon processing tools.

Method Of Forming A Copper Topped Interconnect Structure That Has Thin And Thick Copper Traces

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US Patent:
8324097, Dec 4, 2012
Filed:
Mar 31, 2010
Appl. No.:
12/751894
Inventors:
Abdalla Aly Naem - San Jose CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21/283
US Classification:
438654, 438687, 257E21584, 257E21586
Abstract:
A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide copper traces, on the same chip.

Pocl.sub.3 Process Flow For Doping Polysilicon Without Forming Oxide Pillars Or Gate Oxide Shorts

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US Patent:
58245960, Oct 20, 1998
Filed:
Aug 8, 1996
Appl. No.:
8/689335
Inventors:
Abdalla A. Naem - Sunnyvale CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H02L 2177
US Classification:
438566
Abstract:
In a method of introducing phosphorous from phosphorous oxychloride (POCl. sub. 3) into an undoped gate polysilicon region formed as part of an integrated circuit structure, an initial MOS structure is developed utilizing conventional techniques through the formation of a layer of undoped polysilicon over thin gate oxide. A POCl. sub. 3 layer is then formed over the undoped polysilicon and thermally annealed to drive phosphorous into the gate polysilicon to achieve a desired conductivity level. The phosphorous-rich organic layer is then cleaned from the surface of the POCl. sub. 3 using sulfuric peroxide and the POCl. sub. 3 layer is removed using a DI:HF solution to expose the surface of the doped polysilicon. After formation of a photoresist gate mask, arsenic, or another heavy ion species, is implanted into the exposed polysilicon to amorphized the exposed poly, thereby eliminating the polysilicon grain boundaries. This leads to uniform etching of the amorphized poly and, therefore, disappearance of the oxide pillars.
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Abdalla A Naem from San Jose, CA, age ~73 Get Report