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Aaron K Olbrich

from Morgan Hill, CA
Age ~64
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Also known as:
Aaron Keith Olbrich, Aaron E Olbrich, Aaron C Olbrich, Aaron K Gibrich, Aaron H
Phone and address:
14525 Atherton Cir, Morgan Hill, CA 95037
(408) 683-0555
Related to:
Christal M Olbrich, 63
Connected to:
Brett D Olbrich, 45Christian E Olbrich, 40Courtney L Olbrich, 29Dennis B Olbrich, 64Holli K Olbrich, 42Kimberly D Olbrich, 40Nancy J Olbricht, 73Stefanie O Olbrich, 52Rebecca Olbright, 38David B Olbrisch, 47

Aaron Olbrich Phones & Addresses

  • 14525 Atherton Cir, Morgan Hill, CA 95037 (408) 683-0555
  • 15135 La Rocca Ct, Morgan Hill, CA 95037 (408) 778-1808 (408) 779-8627
  • San Jose, CA
  • Gilroy, CA
  • Santa Clara, CA
  • 14525 Atherton Cir, Morgan Hill, CA 95037 (408) 691-8427

Work

Company: Sandisk May 2011 Position: Senior fellow

Education

Degree: BS School / High School: Washington State University 1979 to 1983 Specialities: Electrical Engineering

Skills

Firmware • Asic • Hardware • Hardware Architecture • Architectures • Embedded Systems • Debugging • Embedded Software • Arm • Algorithms • Microprocessors • C • Soc

Languages

English

Interests

Christianity • Exercise • Gardening • Traveling • Electronics • Home Improvement • Diet • Reading • Fitness • Sports • Family Values • Travel • Home Decoration

Emails

a***[email protected]

Industries

Computer Hardware

Resumes

Resumes

Aaron Olbrich Photo 1

Aaron Olbrich

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Location:
14525 Atherton Cir, Morgan Hill, CA 95037
Industry:
Computer Hardware
Work:
SanDisk since May 2011
Senior Fellow
Pliant Technology Mar 2005 - May 2011
CTO
Fujitsu Computer Products Mar 1998 - Mar 2005
Director Hardware Architecture
IBM Jun 1983 - Mar 1998
Senior Engineer
Education:
Washington State University 1979 - 1983
BS, Electrical Engineering
Skills:
Firmware
Asic
Hardware
Hardware Architecture
Architectures
Embedded Systems
Debugging
Embedded Software
Arm
Algorithms
Microprocessors
C
Soc
Interests:
Christianity
Exercise
Gardening
Traveling
Electronics
Home Improvement
Diet
Reading
Fitness
Sports
Family Values
Travel
Home Decoration
Languages:
English

Business Records

Name / Title
Company / Classification
Phones & Addresses
Aaron Olbrich
Chief Technology Officer
Pliant Technology, Inc.
Plastics Materials, Synthetic Resins, and Non...
630 Alder Dr Ste 202, Milpitas, CA 95035
Aaron Olbrich
Chief Technology Officer
Pliant Technology
Computer Hardware
630 Alder Dr, Milpitas, CA 95035
(408) 321-0320
Aaron Olbrich
Chief Technology Officer
Pliant Technology, Inc.
Plastics Materials, Synthetic Resins, and Non...
630 Alder Dr Ste 202, Milpitas, CA 95035

Publications

Us Patents

Method, System, And Program For Mapping Logical Addresses To High Performance Zones On A Storage Medium

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US Patent:
6502178, Dec 31, 2002
Filed:
Feb 14, 2000
Appl. No.:
09/503279
Inventors:
Aaron Keith Olbrich - Morgan Hill CA
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1200
US Classification:
711202, 711112, 711 4, 711150
Abstract:
Disclosed is a system, method, and program for mapping logical addresses to physical sectors on a storage device including at least one storage medium surface. A determination is made of logical addresses that are specified to be stored in a high throughput region on one storage medium surface. At least two read/write heads operate on the storage medium surface including the high throughput region to increase performance of access operations in the high throughput region. A mapping is generated of the determined logical addresses to the high throughput region. The logical addresses mapped to the high throughput region are capable of being non-contiguous.

Cache Buffer Control Apparatus And Method Using Counters To Determine Status Of Cache Buffer Memory Cells For Writing And Reading Data Therefrom

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US Patent:
6944717, Sep 13, 2005
Filed:
Jul 11, 2002
Appl. No.:
10/193755
Inventors:
Koji Yoneyama - Kawasaki, JP
Yuichi Hirao - Tokyo, JP
Shigeru Hatakeyama - Kawasaki, JP
Aaron Olbrich - Morgan Hill CA, US
Douglas Prins - Laguna Hills CA, US
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G06F012/00
US Classification:
711133, 711156, 711159, 710 57
Abstract:
Methods for controlling and storing data in a cache buffer in a storage apparatus having a nonvolatile memory medium are disclosed. Memory cells are logically divided into a plurality of pages. An open status is registered in a counter for each page that has at least some (and usually all) memory cells available to store new data. A full status is registered in the counter for each page that does not have memory cells that are available to store new data. New data is stored in pages having the open status in the counter. The pages can be weighted according to the read command rate and prioritized for reading and writing purposes.

System And Method For Performing Host Initiated Mass Storage Commands Using A Hierarchy Of Data Structures

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US Patent:
7934052, Apr 26, 2011
Filed:
Apr 8, 2008
Appl. No.:
12/082202
Inventors:
Douglas A. Prins - Laguna Hills CA, US
Aaron K. Olbrich - Morgan Hill CA, US
Assignee:
Pliant Technology, Inc. - Milpitas CA
International Classification:
G06F 12/02
US Classification:
711103, 711E12008
Abstract:
Disclosed is a mass storage system and method for breaking a host command into a hierarchy of data structures. Different types of data structures are designed to handle different phases of tasks required by the host command, and multiple data structures may be used to handle portions of the host command in parallel, thereby allowing increased performance. The disclosed embodiments include a flash memory controller designed to allow a high degree of pipelining and parallelism.

Flash Memory Controller Having Reduced Pinout

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US Patent:
7978516, Jul 12, 2011
Filed:
Apr 8, 2008
Appl. No.:
12/082205
Inventors:
Aaron K. Olbrich - Morgan Hill CA, US
Douglas A. Prins - Laguna Hills CA, US
Assignee:
Pliant Technology, Inc. - Milpitas CA
International Classification:
G11C 11/34
G11C 16/04
US Classification:
36518511, 365191, 711103, 711 5
Abstract:
Disclosed is a flash memory controller connected to a flash memory module. The pin-out of the flash memory controller combines ready-busy and chip-select signals. In one embodiment, the flash memory module is made up of a set of banks, each consisting of a plurality of devices, with each bank sharing a single chip-select/ready-busy connection to the controller.

Patrol Function Used In Flash Storage Controller To Detect Data Errors

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US Patent:
8245101, Aug 14, 2012
Filed:
Apr 8, 2008
Appl. No.:
12/082204
Inventors:
Aaron K. Olbrich - Morgan Hill CA, US
Douglas A. Prins - Laguna Hills CA, US
Assignee:
Sandisk Enterprise IP LLC - Milpitas CA
International Classification:
G06F 11/00
US Classification:
714753, 714 624, 714819, 714758, 714764
Abstract:
A patrol function performed in a storage controller connected to a flash memory storage module. The function causes selected areas of the flash storage to be read for purposes of detecting and correcting errors.

Mlc Self-Raid Flash Data Protection Scheme

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US Patent:
8365041, Jan 29, 2013
Filed:
Mar 17, 2010
Appl. No.:
12/726200
Inventors:
Aaron K. Olbrich - Morgan Hill CA, US
Doug Prins - Laguna Hills CA, US
Assignee:
Sandisk Enterprise IP LLC - Milpitas CA
International Classification:
G11C 29/00
US Classification:
714763, 714801, 711114
Abstract:
A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.

Flash Memory Controller Garbage Collection Operations Performed Independently In Multiple Flash Memory Groups

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US Patent:
8386700, Feb 26, 2013
Filed:
Nov 29, 2011
Appl. No.:
13/306062
Inventors:
Aaron K. Olbrich - Morgan Hill CA, US
Douglas A. Prins - Laguna Hills CA, US
Assignee:
Sandisk Enterprise IP LLC - Milpitas CA
International Classification:
G06F 12/00
US Classification:
711103, 711E12001
Abstract:
A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold.

Mlc Self-Raid Flash Data Protection Scheme

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US Patent:
8473814, Jun 25, 2013
Filed:
Jun 27, 2012
Appl. No.:
13/535250
Inventors:
Aaron K. Olbrich - Morgan Hill CA, US
Doug Prins - Laguna Hills CA, US
Assignee:
SanDisk Enterprise IP LLC - Milpitas CA
International Classification:
G11C 29/00
US Classification:
714763, 36518503
Abstract:
A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.
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Aaron K Olbrich from Morgan Hill, CA, age ~64 Get Report