Search

Weimin M Han

from San Gabriel, CA
Age ~59
Get Report
Also known as:
Weimin Min Han, Wei Min Han, Weimin Ham, Weimin Bymin
Related to:
Weidong Han, 63Jin X Li, 44Pauline C Lu, 63Aileene HanEvelyn Yu, 76
Connected to:
Agnes K Han, 70Ahyoung Han, 37Amber J Han, 48Ami Han, 41Andres S Han, 32Angel B Han, 39Anne E Han, 58Antonio Han, 28Ariel S Han, 46Bae C Han, 70

Weimin Han Phones & Addresses

  • San Gabriel, CA
  • Portland, OR
  • Louisville, KY
  • South El Monte, CA
  • Bend, OR
  • Orange, CA
  • Rosemead, CA
  • Westminster, CA

Resumes

Resumes

Weimin Han Photo 1

Manager

View page
Location:
303 west Newby Ave, San Gabriel, CA 91776
Industry:
Wholesale
Work:
Apis Footwear Co
Manager
Education:
Tsinghua University 1984 - 1992
Master, Engineering
Skills:
Project Management
Product Development
Manufacturing
Global Sourcing
Strategic Planning
Business Strategy
Healthcare
Languages:
English
Weimin Han Photo 2

Engineer Manager

View page
Location:
Portland, OR
Industry:
Research
Work:
Intel Labs
engineer manger
Education:
Oregon State University 1985 - 1991
Doctorates, Doctor of Philosophy, Physics, Philosophy Tsinghua University 1979 - 1985
Bachelors, Physics Beijing #35 Middle School 1974 - 1979
Skills:
Semiconductors
Thin Films
Design of Experiments
Characterization
Semiconductor Industry
Materials Science
Failure Analysis
Spc
Ic
Engineering Management
Statistical Process Control
Jmp
R&D
Manufacturing
Silicon
Weimin Han Photo 3

Weimin Han

View page

Publications

Us Patents

Sidewall Spacers And Methods Of Making Same

View page
US Patent:
20020127763, Sep 12, 2002
Filed:
Dec 28, 2000
Appl. No.:
09/752798
Inventors:
Mohamed Arafa - Chandler AR, US
Weimin Han - Portland OR, US
Alan Myers - Portland OR, US
Daniel Simon - Hillsboro OR, US
International Classification:
H01L021/00
US Classification:
438/076000
Abstract:
L-shaped spacers for use adjacent to the vertical sidewalls of gate electrodes in the manufacture of MOS integrated circuits are described along with methods of fabricating such structures that do not require any additional cost compared to conventional manufacturing processes. A spacer is formed as a tri-layer of silicon oxide/silicon nitride/silicon oxide deposited in- situ at low temperature using a conventional furnace and a bis(tertiarybutylamino) silane chemistry deposition. The spacer has the same performance as a conventional spacer during deep source/drain (S/D) implants. Prior to a cleaning operation which precedes silicidation, the top oxide layer is removed leading to improved gap-fill characteristics. The upper oxide may to removed before deep S/D implantation to further achieve reduction of series resistance.

Deposition Of A Silicon Film

View page
US Patent:
20040152287, Aug 5, 2004
Filed:
Jan 31, 2003
Appl. No.:
10/355964
Inventors:
Adrian Sherrill - Portland OR, US
Weimin Han - Portland OR, US
Pauline Jacob - Portland OR, US
International Classification:
H01L021/20
H01L021/36
C30B001/00
US Classification:
438/485000, 438/486000, 438/488000
Abstract:
An amorphous or polycrystalline silicon film that does not facilitate the reduction of neighboring oxide may be deposited during semiconductor device/integrated circuit fabrication.

Method Of Processing A Substrate

View page
US Patent:
61402516, Oct 31, 2000
Filed:
Dec 10, 1997
Appl. No.:
8/987888
Inventors:
Reza Arghavani - Aloha OR
Robert S. Chau - Beaverton OR
Weimin Han - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2131
H01L 21469
US Classification:
438778
Abstract:
A method of processing a semiconductor substrate, comprising the steps of: heating a substance within a first chamber, at a selected temperature which is above the minimum decomposition temperature of the substance, to cause decomposition of the substance into a predetermined gas; cooling the gas to below the minimum decomposition temperature of the substance; transporting the gas from the first chamber to a second chamber; and exposing a semiconductor substrate, located in the second chamber, to the cooled gas.

Non-Planar Semiconductor Device Having Omega-Fin With Doped Sub-Fin Region And Method To Fabricate Same

View page
US Patent:
20190296114, Sep 26, 2019
Filed:
Jun 7, 2019
Appl. No.:
16/435301
Inventors:
- Santa Clara CA, US
Walid M. HAFEZ - Portland OR, US
Joodong PARK - Portland OR, US
Weimin HAN - Portland OR, US
Raymond E. COTNER - Portland OR, US
Chia-Hong JAN - Portland OR, US
International Classification:
H01L 29/36
H01L 29/66
H01L 27/088
H01L 21/8234
H01L 29/78
Abstract:
Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Apparatus And Methods To Create Microelectronic Device Isolation By Catalytic Oxide Formation

View page
US Patent:
20170162693, Jun 8, 2017
Filed:
Aug 5, 2014
Appl. No.:
15/323726
Inventors:
- Santa Clara CA, US
Walid Hafez - Portland OR, US
Joodong Park - Portland OR, US
Weimin Han - Portland OR, US
Raymond Cotner - Wilsonville OR, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
H01L 29/78
H01L 21/762
H01L 29/66
H01L 29/423
Abstract:
Non-planar transistor devices which include oxide isolation structures formed in semiconductor bodies thereof through the formation of an oxidizing catalyst layer on the semiconductor bodies followed by an oxidation process. In one embodiment, the semiconductor bodies may be formed from silicon-containing materials and the oxidizing catalyst layer may comprise aluminum oxide, wherein oxidizing the semiconductor body to form an oxide isolation zone forms a semiconductor body first portion and a semiconductor body second portion with the isolation zone substantially electrically separating the semiconductor body first portion and the semiconductor body second portion.

Non-Planar Semiconductor Device Having Omega-Fin With Doped Sub-Fin Region And Method To Fabricate Same

View page
US Patent:
20170069725, Mar 9, 2017
Filed:
Jun 26, 2014
Appl. No.:
15/122796
Inventors:
- Santa Clara CA, US
WALID M. HAFEZ - Portland OR, US
JOODONG PARK - Portland OR, US
WEIMIN HAN - Portland OR, US
RAYMOND E. COTNER - Portland OR, US
CHIA-HONG JAN - Portland OR, US
International Classification:
H01L 29/36
H01L 21/8234
H01L 29/66
H01L 27/088
Abstract:
Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Converting A High Dielectric Spacer To A Low Dielectric Spacer

View page
US Patent:
20140175566, Jun 26, 2014
Filed:
Dec 20, 2012
Appl. No.:
13/722561
Inventors:
Gopinath Bhimarasetti - Portland OR, US
Walid M. Hafez - Portland OR, US
Weimin C. Han - Portland OR, US
International Classification:
H01L 29/06
US Classification:
257410, 438595
Abstract:
A dielectric constant of spacer material in a transistor is changed from a high-κ dielectric material to a low-κ dielectric material. The process uses oxidation treatments to enable the transformation of the high-κ dielectric material to a low-κ dielectric material.

Isbn (Books And Publications)

Theoretical Numerical Analysis: A Functional Analysis Framework

View page
Author

Weimin Han

ISBN #

0387215263

Posteriori Error Analysis Via Duality Theory: With Applications In Modeling And Numerical Approximations

View page
Author

Weimin Han

ISBN #

0387235361

Theoretical Numerical Analysis: A Functional Analysis Framework

View page
Author

Weimin Han

ISBN #

0387258876

Theoretical Numerical Analysis: A Functional Analysis Framework

View page
Author

Weimin Han

ISBN #

0387951423

Plasticity: Mathematical Theory and Numerical Analysis

View page
Author

Weimin Han

ISBN #

0387987045

Elementary Numerical Analysis

View page
Author

Weimin Han

ISBN #

0471433373

Quasistatic Contact Problems in Viscoelasticity and Viscoplasticity

View page
Author

Weimin Han

ISBN #

0821831925

Control profile
Weimin M Han from San Gabriel, CA, age ~59 Get Report