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Tan Mai Hoang

from Elk Grove, CA
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Related to:
Danny T Mai, 55Thanh Nam Pham, 64Anh T Vu, 80Hoang T Nguyen, 38Huong T Vu, 69Trang T Hoang, 51Timmy T Mai, 29Van Hoang Pham, 56Mai T Nguyen, 53Theresa Tam Hoang, 29Oanh Pham Hoang, 50Tuyen Thanh MaiKim B Hoang, 36
Connected to:
Angela M Hoang, 41Anhthu H Hoang, 60Anita Hoang, 33Antoine T Hoang, 69Ashlynn N Hoang, 47Biet M Hoang, 56Carolyn Hoang, 37Cathy M Hoang, 47Celeste A Hoang, 40Christopher M Hoang, 54

Tan Hoang Phones & Addresses

  • Elk Grove, CA
  • San Jose, CA
  • Sacramento, CA

Resumes

Resumes

Tan Hoang Photo 1

Business Analyst

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Location:
1266 Lodestone Dr, San Jose, CA 95132
Industry:
Computer Hardware
Work:
Apple since Jul 2008
Business Analyst
Hewlett-Packard Nov 1999 - May 2007
Financial Systems Analyst
Saturn Nov 1993 - Sep 1999
General Ledger Accountant
Education:
San Jose State University 1988 - 1993
Bachelor of Science (BS), Corporate, Finance
Skills:
Payroll
Business Process Improvement
Cross Functional Team Leadership
Vendor Management
Program Management
Management
Leadership
Saas
Business Analysis
Team Leadership
Software Documentation
Sap
Forecasting
Analysis
Process Improvement
Accounting
Project Management
Integration
Customer Service
Microsoft Office
Languages:
English
Mandarin
Tan Hoang Photo 2

Associate Research Analyst

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Location:
United States
Industry:
Environmental Services
Tan Hoang Photo 3

Programer

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Location:
San Jose, CA
Work:
H&T Machining
Programer
Tan Hoang Photo 4

Business Analyst

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Location:
San Francisco, CA
Industry:
Consumer Electronics
Work:
Apple Press Inc.
Business Analyst
Tan Hoang Photo 5

Tan Hoang

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Tan Hoang Photo 6

Tan Hoang San Jose, CA

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Work:
LEOTEK
San Jose, CA
Aug 2014 to Oct 2014
Assembler
DC ELECTRONICS
San Jose, CA
Jul 2009 to May 2011
HOANG'S GARDENING
San Jose, CA
1994 to 2006
Education:
Evergreen Community College
San Jose, CA
English as Second Language
Andrew Hill High School English Program
San Jose, CA
English as Second Language

Publications

Us Patents

Circuit For And Method Of Preventing An Error In A Flip-Flop

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US Patent:
7525362, Apr 28, 2009
Filed:
Mar 17, 2006
Appl. No.:
11/377961
Inventors:
Austin H. Lesea - Los Gatos CA, US
Tan Canh Hoang - Ontario CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 3/356
US Classification:
327208, 327212
Abstract:
A circuit for preventing an error in a flip-flop is disclosed. The circuit comprises an input circuit for receiving input data; a circuit for generating true and complement data associated with each of the input data and redundant data at predetermined nodes of the circuit; and a plurality of inverters each controlled by an associated node, wherein an inverter node of each inverter of the plurality of inverters is coupled to a separate node of the predetermined nodes. A method of preventing an error in a flip-flop is also disclosed.

Memory Array With Multiple-Event-Upset Hardening

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US Patent:
7795900, Sep 14, 2010
Filed:
Jun 16, 2009
Appl. No.:
12/485241
Inventors:
Austin H. Lesea - Los Gatos CA, US
Tan C. Hoang - New Almaden CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19/003
US Classification:
326 9, 326101, 365 54
Abstract:
An integrated circuit has a memory array with a four-plex of SEU-hardened memory cells. Each of the SEU-hardened memory cells has an orientation different from each of the other SEU-hardened memory cells in the four-plex, and each of the SEU-hardened memory cells has a different critical ion track. Providing a four-plex of SEU-hardened memory cells, each with a different critical ion track, reduces the probability of a single ion upsetting adjacent memory cells.
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Tan Mai Hoang from Elk Grove, CA Get Report