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Qi M Wu

from San Jose, CA
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Related to:
Lingqi Wu, 39Shin Liu YishinAili L Wu, 70George I Wu, 73Li WuLi P Hao, 73Jen Wu Yi, 65Betty R Hau, 78Lei Yin, 62Sue C Hao, 46
Connected to:
Aihua Wu, 40Ailsa T Wu, 53Alice H Wu, 55Alix S Wu, 52Amie Wu, 39Angela Y Wu, 72Anqi Wu, 44Anqiang Wu, 48Banting H Wu, 63Baodong Wu, 62

Qi Wu Phones & Addresses

  • San Jose, CA

Resumes

Resumes

Qi Wu Photo 1

Mechanical Engineer

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Location:
San Francisco, CA
Industry:
Mechanical Or Industrial Engineering
Work:
Foxconn
Mechanical Engineer
Applied Seals North America Nov 2013 - Sep 2014
Mechanical Engineer
Hantel Technologies, Inc. Feb 2013 - Oct 2013
Mechanical Engineer I
Indicate Technologies, Inc. Aug 2012 - May 2013
Quality Inspector
Jpmorgan Chase & Co. Feb 2011 - Aug 2012
Teller
Education:
San Jose State University 2011 - 2014
Master of Science, Masters, Mechanical Engineering University of California, Davis 2006 - 2010
Bachelors, Engineering, Mechanical Engineering
Skills:
Solidworks
Finite Element Analysis
Inspection
Ptc Pro/Engineer
Pro/Mechanica
Six Sigma
Mechanical Engineering
Automotive
Troubleshooting
Microsoft Excel
Banking
Powerpoint
Microsoft Word
Metrology
Mechatronics
Pid
Arduino
Interests:
Aerospace
Automotive
Movie
Snowboarding
New Technologies
Music
Running
Computer Troubleshooting
Food
Gym
Languages:
Mandarin
Cantonese
English
Qi Wu Photo 2

Director, Software Engineering

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Location:
San Francisco, CA
Industry:
Computer Hardware
Work:
Scaleflux
Director, Software Engineering
Apple Mar 2014 - Aug 2015
Ssd Architect
Skyera Jan 2012 - Mar 2014
Principal Engineer
Rensselaer Polytechnic Institute Aug 2008 - Dec 2011
Research Assistant
O2Micro Jul 2006 - Jul 2008
Asic Design Engineer
Education:
Rensselaer Polytechnic Institute 2008 - 2011
Doctorates, Doctor of Philosophy, Electrical Engineering Xi'an Jiaotong University 2003 - 2006
Masters Xi'an Jiaotong University 1999 - 2003
Bachelors
Skills:
Asic
Application Specific Integrated Circuits
Certifications:
Professional Leadership Certification
Rensselaer Polytechnic Institute
Qi Wu Photo 3

Carnage Middle School

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Work:
United States
Carnage Middle School
Qi Wu Photo 4

Qi Wu

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Qi Wu Photo 5

Advisor

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Work:

Advisor
Qi Wu Photo 6

Qi Wu

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Work:
Rensselaer Polytechnic Institute

Aug 2008 to Present
Research Assistant
Xi'an Jiaotong University
Xi'an, China
Sep 2005 to Jul 2006
Research Assistant
O2Micro
Santa Clara, CA
ASIC Designer
Education:
Rensselaer Polytechnic Institute
Troy, NY
Jan 2008 to Jan 2012
Ph.D. in Electrical Engineering
Xi'an Jiaotong University
Xi'an, China
Jan 2003 to Jan 2006
Master of Engineering in Electrical Engineering
Xi'an Jiaotong University
Xi'an, China
Jan 1999 to Jan 2003
Bachelor in Electrical Engineering
Skills:
Programming Language: Verilog/VHDL, C/C++, Matlab, Perl, and Tcl. Tools: VCS, De- sign Compiler, PrimeTime, Formality, ModelSim, Cadance, Hspice, CustomExplorer, Synplify, Quartus, Protel, M5 full system simulator, HotSpot thermal simulator, and DiskSim disk simu- lator.
Qi Wu Photo 7

Qi (Edward) Wu San Jose, CA

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Work:
Applied Seals North America Inc

Nov 2013 to 2000
Mechanical Engineer
Hantel Technologies Inc

Feb 2013 to Oct 2013
Mechanical Engineer I Intern
Indicate Technologies Inc

Aug 2012 to May 2013
Inspector
Education:
San Jose State University
San Jose, CA
May 2014
M.S. in Mechanical Engineering
University of California
Davis, CA
Sep 2010
B.S. in Mechanical and Aeronautical Engineering
Skills:
Fluent in Chinese (both Mandarin and Cantonese), SolidWorks, Pro/E, AutoCAD, MATLAB, MATLAB Simulink, FEA, nonlinear analysis, polymer, classic control, feedback control, Arduino, PID control, Inspection, GD&T Y14.5-2009, CMM measuring, machine shop, injection molding, compression molding
Qi Wu Photo 8

Qi Wu Stanford, CA

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Work:
China Development Bank Headquarters

Jun 2012 to Sep 2012
Account Manager Assistant
AECOM

Jun 2011 to Sep 2011
Structural Engineer Intern
University of Michigan
Ann Arbor, MI
May 2010 to Aug 2010
Lab Assistant
University of Michigan
Ann Arbor, MI
Sep 2009 to May 2010
Design Leader
Shanghai International Technology & Trade United Co., Ltd

Dec 2007 to Feb 2008
Engineer Intern
Education:
Stanford University
Stanford, CA
Sep 2011 to 2000
M.S. in Structural Engineering and Geomechanics
Shanghai Jiao Tong University
Sep 2007 to Aug 2011
B.S.E. in Mechanical Engineering
University of Michigan
Ann Arbor, MI
Sep 2009 to Apr 2011
B.S.E. in Civil and Environmental Engineering
Skills:
COURSES Stanford University Advanced Structural Analysis (CEE280) Nonlinear Structural Analysis (CEE282) Structural Dynamics (CEE283) Advanced Structural Concrete Behavior and Design (CEE285A) Advanced Structural Steel Behavior and Design (CEE285B) Probabilistic Modeling in Civil Engineering (CEE203) Structural Reliability (CEE204) Earthquake Hazard and Risk Analysis (CEE288) Life Cycle Assessment for Complex Systems (CEE226) Programming Methodology Java (CS106A) Building Information Modeling (CEE210) Global Infrastructure Projects (CEE241C) Stochastic Modeling (MS&E 221) University of Michigan Structural Engineering (CEE312) Fluid Mechanics (CEE325) Civil Engineering Materials (CEE351) Computational Methods for Engineers and Scientists (CEE303) Geotechnical Engineering (CEE345) Design of Reinforced Concrete Structures (CEE415) Design of Metal Structures (CEE413) Sustainable Engineering Principles (CEE265) Environmental Engineering Principles (CEE365) Hydrology and Floodplain Hydraulics (CEE421) Construction of Buildings (CEE537) Professional Issues and Designs (CEE402) Construction Contracting (CEE431)

Business Records

Name / Title
Company / Classification
Phones & Addresses
Qi Xing Wu
ORIENTAL PEARL RESTAURANT LLC

Publications

Isbn (Books And Publications)

China

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Author

Qi Wu

ISBN #

0844247561

Beijing: William Lindesay and Wu Qi

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Author

Qi Wu

ISBN #

0844247685

Us Patents

Low-Cost Address Mapping For Storage Devices With Built-In Transparent Compression

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US Patent:
20220188225, Jun 16, 2022
Filed:
Dec 14, 2020
Appl. No.:
17/120386
Inventors:
- San Jose CA, US
Qi Wu - San Jose CA, US
International Classification:
G06F 12/06
G06F 7/08
G06F 3/06
G06F 11/07
Abstract:
An infrastructure for mapping between logic block addresses (LBAs) and physical block addresses (PBAs). A disclosed method includes: receiving a request the specifies an LBA; determining an applicable zone based on the LBA from a set of zones, wherein the set of zones expose an LBA address space of the storage device; identifying at least one tree from a set of trees having a root node associated with the applicable zone; traversing the at least one tree to identify a set of leaf nodes based on the LBA, wherein each leaf node points to an mpage; and determining corresponding PBA information for the LBA by examining mapping information contained in each mpage.

Realizing High-Speed And Low-Latency Raid Across Multile Solid-State Storage Device With Host-Side Ftl

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US Patent:
20200034234, Jan 30, 2020
Filed:
Jul 25, 2019
Appl. No.:
16/521703
Inventors:
- San Jose CA, US
Qi Wu - San Jose CA, US
International Classification:
G06F 11/10
G06F 12/10
Abstract:
A method for implementing a RAID group in a system including a host computing system, a first set of storage devices for storing user data for the RAID group, and a second set of storage devices for storing redundancy data for the RAID group. The method includes: distributing the user data from a host-side FLT module on the host computing system to the first set of storage devices; determining, by each storage device in the first set of storage devices, a logical block address to physical block address (LBA-PBA) binding for the user data received from the host-side FLT module; sending LBA-PBA binding information for the LBA-PBA binding from the first set of storage devices to the host-side FLT module; and performing, by the host-side FLT module, RAID encoding to form the RAID group based on the LBA-PBA binding information received from the first set of storage devices.

Using Hybrid-Software/Hardware Based Logical-To-Physical Address Mapping To Improve The Data Write Throughput Of Solid-State Data Storage Devices

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US Patent:
20200034286, Jan 30, 2020
Filed:
Jul 25, 2019
Appl. No.:
16/521711
Inventors:
- San Jose CA, US
Qi Wu - San Jose CA, US
International Classification:
G06F 12/02
G06F 3/06
G06F 12/0802
G06F 12/1009
Abstract:
The present disclosure relates to the field of solid-state data storage, and particularly to improving the write throughput performance of solid-state data storage devices. A method for providing logical block address (LBA) to physical block address (PBA) binding in a storage device includes: receiving at least one thread at a hardware engine of the device controller of the storage device, each thread including data and LBAs for the data; writing the data into a write buffer of the storage device; binding, by the hardware engine of the device controller, a sequence of contiguous PBAs for a section of the memory to the LBAs for the data in the write buffer; determining if the write buffer contains enough data for the section of the memory; and if the write buffer contains enough data for the section of the memory, writing the data to the section of the memory.

Reducing Solid State Storage Device Read Tail Latency

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US Patent:
20190056870, Feb 21, 2019
Filed:
Aug 15, 2018
Appl. No.:
15/998430
Inventors:
- San Jose CA, US
Jinjin He - Santa Clara CA, US
Qi Wu - San Jose CA, US
International Classification:
G06F 3/06
Abstract:
A storage device, infrastructure, and associated method for managing request queue to reduce read tail latencies. A disclosed storage device is disclosed that includes: a set of flash memory chips; and a controller that schedules request from a host using a set of request queues, wherein the controller includes a queue manager that: reorders high priority read requests over low priority write requests in each request queue; suspends low priority write requests to process high priority read requests; and limits a number of low priority write requests allowed in each request queue to a threshold value smaller than a size of each request queue.

Apparatus And Method For Using Fields In N-Space Translation Of Storage Requests

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US Patent:
20170344303, Nov 30, 2017
Filed:
Mar 14, 2017
Appl. No.:
15/458945
Inventors:
- San Jose CA, US
Ladislav STEFFKO - San Ramon CA, US
Qi WU - San Jose CA, US
International Classification:
G06F 3/06
G06F 12/1027
G06F 17/30
G06F 12/10
G06F 12/1018
G06F 12/02
Abstract:
A translation system can translate a request having multiple fields to a physical address using the fields as indexes to a multi-dimensional graph. A field or portion of a field can represent a location along an axis. When combined together, the fields can represent a point in n-space, where n is the number of axes. In some embodiments, a nearest neighbor calculation can be sufficient along an axis. Therefore, a point in n-space defined by the fields can be translated along an axis until a nearest neighbor entry is determined. When the entry is determined, the entry can be accessed to determine a correct response to the translation request.

Apparatus And Method For Insertion And Deletion In Multi-Dimensional To Linear Address Space Translation

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US Patent:
20170199826, Jul 13, 2017
Filed:
Mar 27, 2017
Appl. No.:
15/470695
Inventors:
- San Jose CA, US
Ladislav STEFFKO - San Ramon CA, US
Qi WU - San Jose CA, US
International Classification:
G06F 12/1018
G06F 17/30
G06F 12/02
G06F 12/1027
G06F 3/06
Abstract:
A translation system can translate a storage request to a physical address using fields as keys to traverse a map of nodes with node entries. A node entry can include a link to a next node or a physical address. Using a portion of the key as noted in node metadata, a node entry can be determined. When adding node entries to a node, a node utilization can exceed a threshold value. A new node can be created such that node entries are split between the original and new node. Node metadata of the parent node, new node and original node can be revised to identify which parts of the key are used to identify a node entry. When removing node entries from a node, node utilization can cross a minimum threshold value. Node entries from the node can be merged with a sibling, or the map can be rebalanced.

Writable Clone Data Structure

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US Patent:
20160147474, May 26, 2016
Filed:
Feb 1, 2016
Appl. No.:
15/012260
Inventors:
- San Jose CA, US
Qi WU - San Jose CA, US
International Classification:
G06F 3/06
Abstract:
A memory system including parent data and clone data is disclosed, where the clone data represents a clone of the parent data. The system determines whether clone data to be accessed is different from corresponding data in the parent. The system also determines a physical location of the data to be accessed based on whether the data to be accessed is different from the corresponding parent data. The system also accesses the data based on the physical location.

Writable Clone Data Structure

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US Patent:
20160147475, May 26, 2016
Filed:
Feb 1, 2016
Appl. No.:
15/012294
Inventors:
- San Jose CA, US
Qi WU - San Jose CA, US
International Classification:
G06F 3/06
Abstract:
A memory system including parent data and clone data is disclosed, where the clone data represents a clone of the parent data. The system determines whether clone data to be accessed is different from corresponding data in the parent. The system also determines a physical location of the data to be accessed based on whether the data to be accessed is different from the corresponding parent data. The system also accesses the data based on the physical location.
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Qi M Wu from San Jose, CA Get Report