May Zar Lin

7779164, Aug 17, 2010

Apr 4, 2005

11/098213

Ariel Hendel - Cupertino CA, US
Yatin Gajjar - Fremont CA, US
May Lin - Saratoga CA, US
Rahoul Puri - Los Altos CA, US
Michael Wong - Cupertino CA, US

Oracle America, Inc. - Redwood City CA

G06F 15/16
G06F 17/30
H04J 3/00

709250, 707711, 370464

A network system includes a network interface unit operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. In various embodiments of the invention, predetermined subsets of the plurality of processing entities are operably associated with predetermined subsets of the plurality of memory units thereby defining a plurality of asymmetrical data processing partitions. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing partitions. The asymmetrical data processing partitions are scalable by adding additional processing entities.

7889734, Feb 15, 2011

Apr 5, 2005

11/098063

Ariel Hendel - Cupertino CA, US
Yatin Gajjar - Fremont CA, US
May Lin - Saratoga CA, US
Rahoul Puri - Los Altos CA, US
Michael Wong - Cupertino CA, US

Oracle America, Inc. - Redwood City CA

H04L 12/28

370392

A method and apparatus for mapping sessions to preassigned processing entities in a network system. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. In various embodiments of the invention, predetermined subsets of the plurality of processing entities are operably associated with predetermined subsets of the plurality of memory units thereby defining a plurality of asymmetrical data processing partitions. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing partitions based upon an association with a predetermined session. In various embodiments of the invention, the asymmetrical data processing partitions can comprise a plurality of processor cores, a single processor core, a combination of strands of an individual processor core or a single strand of an individual processor core.

7992144, Aug 2, 2011

Apr 4, 2005

11/098195

Ariel Hendel - Cupertino CA, US
Yatin Gajjar - Fremont CA, US
May Lin - Saratoga CA, US
Rahoul Puri - Los Altos CA, US
Michael Wong - Cupertino CA, US

Oracle America, Inc. - Redwood City CA

G06F 15/16
G06F 9/455

718 1, 709250

A network system that provides for separating and isolating control of processing entities in a network interface. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. One of the processing entities operates as a hypervisor to configure control resources to isolate operation of the plurality of data processing partitions to process data transported by the network system. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing. In various embodiments of the invention, the asymmetrical data processing partitions can comprise a plurality of processor cores, a single processor core, a combination of strands of an individual processor core or a single strand of an individual processor core.

8510491, Aug 13, 2013

Apr 5, 2005

11/098727

Ariel Hendel - Cupertino CA, US
Yatin Gajjar - Fremont CA, US
May Lin - Saratoga CA, US
Rahoul Pun - Los Altos CA, US
Michael Wong - Cupertino CA, US

Oracle America, Inc. - Redwood City CA

G06F 13/24
G06F 13/32
G06F 3/00
G06F 5/00
G06F 13/00
G06F 13/28
G06F 15/167

710260, 710 50, 710269, 711129, 711148, 711173, 709214, 709215

A method and apparatus for efficient interrupt event notification for a scalable input/output device in a network system. A network interface unit is operably connected to a plurality of processing entities and associated memory units. At least one status register in the network interface unit contains information relating to a process to be performed by at least one processing entity communicated to the processing entity by an interrupt event notification. Shared memory space comprises a mailbox storage register operable to store an image of the interrupt information stored in the status register of the network interface unit. A processing entity can directly access the process information stored in the mailbox status register thereby reducing system latency associated with reading information in the status register. Updated process status information in the network interface status register may be read by the processing entity on an interleaved basis while executing a process.

20060251109, Nov 9, 2006

Apr 5, 2005

11/098310

Shimon Muller - Sunnyvale CA, US
Ariel Hendel - Cupertino CA, US
Yatin Gajjar - Fremont CA, US
Michael Wong - Cupertino CA, US
Rahoul Puri - Los Altos CA, US
May Lin - Saratoga CA, US

H04L 12/66

370463000

A network system which includes a plurality of processing entities, an interconnect device coupled to the plurality of processing entities, a memory system coupled to the interconnect device and the plurality of processing entities, a network interface unit coupled to the plurality of processing entities and the memory system via the interconnect device. The network interface includes a memory access module and a packet classifier. The memory access module includes a plurality of parallel memory access channels. The packet classifier provides a flexible association between packets and the plurality of processing entities via the plurality of memory access channels.