Kent D Moat

6850536, Feb 1, 2005

Jun 28, 2002

10/184609

Philip E. May - Palatine IL, US
Kent Donald Moat - Winfield IL, US
Silviu Chiricescu - Chicago IL, US
Brian Geoffrey Lucas - Barrington IL, US
James M. Norris - Naperville IL, US

Motorola, Inc. - Schaumburg IL

H04L 1250
H04L 1254
H03M 1300

370428, 370383, 370392, 37039571, 710 4, 714776

An interconnection device () with a number of links (and ), each link having a number of link input ports (), link output ports () and storage registers (). An input selection switch () is coupled to a selected link input port to receive an input data token. The storage registers () may be used to store input data tokens. A storage access switch () is coupled to the input selection switch () and to the storage registers () and may be used to select the current input data token or a token from the storage registers as an output data token. An output selection switch () receives the output data token and provides it to a selected link output port. The interconnection device may, for example, be used to connect the inputs and outputs of the processing elements of a vector processor or digital signal processor.

6934938, Aug 23, 2005

Jun 28, 2002

10/184743

Philip E. May - Palatine IL, US
Kent Donald Moat - Winfield IL, US
Silviu Chiricescu - Chicago IL, US
Brian Geoffrey Lucas - Barrington IL, US
James M. Norris - Naperville IL, US
Michael Allen Schuette - Wilmette IL, US
Ali Saidi - Cambridge MA, US

Motorola, Inc. - Schaumburg IL

G06F009/44

717132, 717100, 717106, 717133, 717156, 712 7, 712 8, 712201, 708490

A method for producing a formatted description of a computation representable by a data-flow graph and computer for performing a computation so described. A source instruction is generated for each input of the data-flow graph, a computational instruction is generated for each node of the data-flow graph, and a sink instruction is generated for each output of the data-flow graph. The computational instruction for a node includes a descriptor of an operation performed at the node and a descriptor of each instruction that produces an input to the node. The formatted description is a sequential instruction list comprising source instructions, computational instructions and sink instructions. Each instruction has an instruction identifier and the descriptor of each instruction that produces an input to the node is the instruction identifier. The computer is directed by a program of instructions to implement a computation representable by a data-flow graph.

7100019, Aug 29, 2006

Sep 8, 2003

10/657793

James M. Norris - Naperville IL, US
Philip E. May - Palatine IL, US
Kent D. Moat - Winfield IL, US
Brian G. Lucas - Barrington IL, US

Motorola, Inc. - Schaumburg IL

G06F 15/00
G06F 12/00

712 7, 712 6, 711213, 711217, 711219, 711220

A system and method for calculating memory addresses in a partitioned memory in a processing system having a processing unit, input and output units, a program sequencer and an external interface. An address calculator includes a set of storage elements, such as registers, and an arithmetic unit for calculating a memory address of a vector element dependent upon values stored in the storage elements and the address of a previous vector element. The storage elements hold STRIDE, SKIP and SPAN values and optionally a TYPE value, relating to the spacing between elements in the same partition, the spacing between elements in the consecutive partitions, the number of elements in a partition and the size of a vector element, respectively.

7140019, Nov 21, 2006

Jun 28, 2002

10/184772

Philip E. May - Palatine IL, US
Kent Donald Moat - Winfield IL, US
Silviu Chiricescu - Chicago IL, US
Brian Geoffrey Lucas - Barrington IL, US
James M. Norris - Naperville IL, US
Michael Allen Schuette - Wilmette IL, US
Ali Saidi - Cambridge MA, US

Motorola, inc. - Schaumburg IL

G06F 9/50
G06F 9/44

718102, 718105, 718104

A method for scheduling a computation for execution on a computer with a number of interconnected functional units. The computation is representable by a data-flow graph with a number of nodes connected by edge. A loop-period of the computation is calculated and the nodes are scheduled for throughput by assigning an execution cycle and a functional unit to each node of the data-flow graph. The scheduling of flexible nodes is adjusted to minimize the number of interconnections required in each execution cycle. The edges of the data-flow graph are allocated to one or more of the interconnections between functional units. The scheduling method may be used, for example, to optimize the interconnection fabric design for an ASIC or as part of a compiler for a re-configurable streaming vector processor.

7159099, Jan 2, 2007

Jun 28, 2002

10/184583

Brian Geoffrey Lucas - Barrington IL, US
Philip E. May - Palatine IL, US
Kent Donald Moat - Winfield IL, US
Silviu Chiricescu - Chicago IL, US
James M. Norris - Naperville IL, US
Michael Allen Schuette - Wilmette IL, US
Ali Saidi - Cambridge MA, US

Motorola, Inc. - Schaumburg IL

G06F 15/00

712218, 712 2, 712 15, 712 37, 712 43, 712229, 712245

A re-configurable, streaming vector processor () is provided which includes a number of function units (), each having one or more inputs for receiving data values and an output for providing a data value, a re-configurable interconnection switch () and a micro-sequencer (). The re-configurable interconnection switch () includes one or more links, each link operable to couple an output of a function unit () to an input of a function unit () as directed by the micro-sequencer (). The vector processor may also include one or more input-stream units () for retrieving data from memory. Each input-stream unit is directed by a host processor and has a defined interface () to the host processor. The vector processor also includes one or more output-stream units () for writing data to memory or to the host processor. The defined interface of the input-stream and output-stream units forms a first part of the programming model. The instructions stored in a memory, in the sequence that direct the re-configurable interconnection switch, form a second part of the programming model.

7219209, May 15, 2007

Aug 29, 2003

10/652137

Kent D. Moat - Winfield IL, US

Motorola, Inc. - Schaumburg IL

G06F 12/10

711202, 711207

A bus filter includes a first bus interface connected to a system bus for receiving a virtual memory address and a second interface connected to the system bus for transmitting a physical memory address. In operation, an address translation unit, such as a translation lookaside buffer, determines the physical memory address from the virtual memory address. The bus filter may be used to couple a processing device, such as an accelerator, to a system having a core processor and an external memory unit coupled by a bus.

7246203, Jul 17, 2007

Nov 19, 2004

10/993972

Kent D. Moat - Winfield IL, US
Philip E. May - Palatine IL, US
James M. Norris - Naperville IL, US

Motorola, Inc. - Schaumburg IL

G06F 12/00

711133, 711134, 711135, 711137

A cache for storing data elements is disclosed. The cache includes a cache memory having one or more lines and one or more cache line counters, each associated with a line of the cache memory. In operation, a cache line counter of the one or more of cache line counters is incremented when a request is received to prefetch a data element into the cache memory and is decremented when the data element is consumed. Optionally, one or more reference queues may be used to store the locations of data elements in the cache memory. In one embodiment, data cannot be evicted from cache lines unless the associated cache line counters indicate that the prefetched data has been consumed.

7275148, Sep 25, 2007

Sep 8, 2003

10/657797

William C. Moyer - Dripping Springs TX, US
James M. Norris - Naperville IL, US
Philip E. May - Palatine IL, US
Kent Donald Moat - Winfield IL, US
Brian Geoffrey Lucas - Barrington IL, US

Freescale Semiconductor, Inc. - Austin TX

G06F 9/312
G06F 15/80

712225, 712 22

Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum number of vector elements that may be transferred to or from a single register within a register file. Also, the instructions may use a variety of different addressing modes. The memory element size may be specified independently from the register element size such that source and destination sizes may differ within an instruction. With some instructions, a vector stream may be initiated and conditionally enqueued or dequeued. Truncation or rounding fields may be provided such that source data elements may be truncated or rounded when transferred. Also, source data elements may be sign- or unsigned-extended when transferred.