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Joyce C Sum

from Cupertino, CA
Age ~72
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Related to:
Kyle C SumCharles P SumEric Sum, 35
Connected to:
Beverly J Sum, 59Chan Sum, 51Deborah A Sum, 76Hui Sum, 125Kelsey N Sum, 33Kenneth Sum, 76Kwai Y Sum, 50Lap W Sum, 62Mary K Sum, 75

Joyce Sum Phones & Addresses

  • 10179 Byerly Ct, Cupertino, CA 95014 (408) 996-1883 (408) 396-6786
  • Cherry Hill, NJ
  • San Jose, CA
  • Carmel, CA
  • Seattle, WA

Publications

Us Patents

Method For Fabricating An Interconnect Structure With Hard Mask And Low Dielectric Constant Materials

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US Patent:
60279958, Feb 22, 2000
Filed:
Aug 18, 1998
Appl. No.:
9/135618
Inventors:
Chien Chiang - Fremont CA
Chuanbin Pan - Santa Clara CA
Vicky M. Ochoa - Pleasanton CA
Sychyi Fang - Palo Alto CA
David B. Fraser - Danville CA
Joyce C. Sum - Cupertino CA
Gary William Ray - Mountain View CA
Jeremy A. Theil - Menlo Park CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2128
US Classification:
438623
Abstract:
An interconnect system is provided. The interconnect system includes a silicon substrate and a first dielectric layer formed upon the silicon substrate. The interconnect system also includes a first level of at least two electrically conductive lines formed upon the first dielectric layer. The interconnect system further includes a region of low dielectric constant material formed between the at least two electrically conductive lines. The interconnect system also includes a first hard mask formed upon the polymer region.

Interconnect Structure With Hard Mask And Low Dielectric Constant Materials

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US Patent:
58864105, Mar 23, 1999
Filed:
Jun 26, 1996
Appl. No.:
8/670624
Inventors:
Chien Chiang - Fremont CA
Chuanbin Pan - Santa Clara CA
Vicky M. Ochoa - Pleasanton CA
Sychyi Fang - Palo Alto CA
David B. Fraser - Danville CA
Joyce C. Sum - Cupertino CA
Gary William Ray - Mountain View CA
Jeremy A. Theil - Menlo Park CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23485
US Classification:
257759
Abstract:
An interconnect system is provided. The interconnect system includes a silicon substrate and a first dielectric layer formed upon the silicon substrate. The interconnect system also includes a first level of at least two electrically conductive lines formed upon the first dielectric layer. The interconnect system further includes a region of low dielectric constant material formed between the at least two electrically conductive lines. The interconnect system also includes a first hard mask formed upon the polymer region.
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Joyce C Sum from Cupertino, CA, age ~72 Get Report