Joseph Neil Kryzak from Winter Garden, FL, age 55

Resumes

Joseph Kryzak

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Business Records

Name / Title

Company / Classification

Phones & Addresses

Joseph N. Kryzak
Chief Executive Officer

Aligned Services Incorporated
Services-Misc · Software and Hardware Developer

2059 Camden Ave, San Jose, CA 95124

Publications

Us Patents

16B/20B Encoder

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US Patent:

6617984, Sep 9, 2003

Filed:

Sep 6, 2002

Appl. No.:

10/236603

Inventors:

Joseph Neil Kryzak - Ames IA
Thomas E. Rock - Richmond IL

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03M 700

US Classification:

341 59, 341 58, 341 61, 341 57, 341 60, 341 62, 341 63, 341 64

Abstract:

A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Scalable Physical Coding Sublayer (Pcs) And 8B/10B Encoder

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US Patent:

6700510, Mar 2, 2004

Filed:

Nov 13, 2002

Appl. No.:

10/294212

Inventors:

Joseph Neil Kryzak - Ames IA
Thomas E. Rock - Richmond IL

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03M 700

US Classification:

341 59, 341 58, 341 61, 341102, 341103

Abstract:

A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use B/ B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of B/ B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Enhanced 8B/10B Encoding/Decoding And Applications Thereof

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US Patent:

6812870, Nov 2, 2004

Filed:

Sep 11, 2003

Appl. No.:

10/660191

Inventors:

Joseph Neil Kryzak - Ames IA
Charles W. Boecker - Ames IA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03M 700

US Classification:

341 95, 341 58

Abstract:

8b/10b encoding begins when an input running disparity is received. The processing then continues by receiving an 8-bit digital input that includes a 5-bit digital input portion and a 3-bit digital input portion. The processing then continues by determining, in parallel, a 6-bit running disparity and a 4-bit running disparity. The processing then continues by determining a 6-bit digital output based on the 6-bit running disparity and the 5-bit digital input portion. The processing then continues by determining a 4-bit digital output based on the 4-bit running disparity and the 3-bit digital input portion. The resulting 10-bit encoded digital output is the combination of the 6-bit digital output and the 4-bit digital output.

Integrated Circuit With Auto Negotiation

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US Patent:

6976102, Dec 13, 2005

Filed:

Sep 11, 2003

Appl. No.:

10/660159

Inventors:

Eric D. Groen - Ankeny IA, US
Charles W. Boecker - Ames IA, US
William C. Black - Ames IA, US
Scott A. Irwin - Ames IA, US
Joseph N. Kryzak - Ames IA, US
Aaron J. Hoelscher - Ankeny IA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F013/38

US Classification:

710 72, 710105, 710100, 710106, 326 38

Abstract:

Method and apparatus for auto-negotiation of a programmable logic device for any of a plurality of communication protocols is described. The programmable logic device is programmed for auto negotiation to establish a communication session. The programmable logic device has access to transceiver attributes. A portion of the transceiver attributes are selected in response to session information from the auto negotiation. The portion of the transceiver attributes selected are for configuring at least one transceiver for a communication protocol.

Programmable Logic Device Including Programmable Multi-Gigabit Transceivers

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US Patent:

7406118, Jul 29, 2008

Filed:

Sep 11, 2003

Appl. No.:

10/661016

Inventors:

Eric D. Groen - Ankeny IA, US
Charles W. Boecker - Ames IA, US
William C. Black - Ames IA, US
Scott A. Irwin - Ames IA, US
Joseph N. Kryzak - Ames IA, US
Yiqin Chen - Ames IA, US
Andrew G. Jenkins - Nevada IA, US
Aaron J. Hoelscher - Ankeny IA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04B 1/38

US Classification:

375219

Abstract:

A programmable logic device includes a plurality of programmable multi-gigabit transceivers, programmable logic fabric, and a control module. Each of the plurality of programmable multi-gigabit transceivers is individually programmed to a desired transceiving mode of operation in accordance with a plurality of transceiver settings. The programmable logic fabric is operably coupled to the plurality of programmable multi-gigabit transceivers and is configured to process at least a portion of the data being transceived via the multi-gigabit transceivers. The control module is operably coupled to produce the plurality of transceiver settings based on a desired mode of operation for the programmable logic device.

Channel Bonding Of A Plurality Of Multi-Gigabit Transceivers

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US Patent:

7421014, Sep 2, 2008

Filed:

Sep 11, 2003

Appl. No.:

10/659974

Inventors:

Joseph Neil Kryzak - Ames IA, US
Aaron J. Hoelscher - Ankeny IA, US
Thomas E. Rock - Richmond IL, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H04B 1/38
H04L 5/16

US Classification:

375219, 375222, 375220, 370535, 455 73, 455 88, 455507

Abstract:

A method for channel bonding begins when a master transceiver receives a channel bonding sequence. The process continues with the master transceiver generating a channel bonding request and transmitting it and channel bonding configuration information to the slave transceiver. The process continues with each slave receiving the channel bonding sequence, the channel bonding request and the channel bonding configuration information. The process continues as each slave processes the channel bonding request and the channel bonding sequence in accordance with the channel bonding configuration information to determine individual slave channel bonding start information. The process continues as the master processes the channel bonding sequence in accordance with the channel bonding configuration information and the channel bonding request to determine master channel bonding start information.

Variable Latency Buffer And Method Of Operation

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US Patent:

7519747, Apr 14, 2009

Filed:

Sep 11, 2003

Appl. No.:

10/660449

Inventors:

Warren E. Cory - Redwood City CA, US
Joseph Neil Kryzak - San Jose CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G06F 5/06
G06F 3/00
G06F 3/06

US Classification:

710 53, 710 52, 710 54, 710 57

Abstract:

A variable latency elastic buffer comprises a plurality of memory locations in which to hold data. A write and read pointer may point to respective write and read addresses of the plurality of locations in which to write and read data. A controller may hold or increment the address of the read pointer upon determining that the amount of data within the buffer differs from a nominal fill level. In a particular embodiment, initialization circuitry may be operable to initialize the read and write addresses of the respective pointers responsive to an initialization request. The read and write addresses may differ from one another by an offset value equal to a value programmed for the nominal value.

Framing Of Transmit Encoded Data And Linear Feedback Shifting

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US Patent:

7724903, May 25, 2010

Filed:

Mar 20, 2008

Appl. No.:

12/052699

Inventors:

Joseph Neil Kryzak - San Jose CA, US
Aaron J. Hoelscher - Ankeny IA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H04L 9/00
H04K 1/00

US Classification:

380265, 380259, 380255

Abstract:

Framing transmit encoded output data begins by determining a scrambling remainder between scrambling of an input code word in accordance with a 1scrambling protocol and the scrambling of the input code word in accordance with an adjustable scrambling protocol. The processing continues by adjusting the adjustable scrambling protocol based on the scrambling remainder to produce an adjusted scrambling protocol. The processing then continues by scrambling the input code word in accordance with the 1scrambling protocol to produce a 1scrambled code word. The processing continues by scrambling the input code word in accordance with the adjusted scrambling protocol to produce a scrambled partial code word. The processing continues by determining a portion of the 1scrambled code word based on the scrambling remainder. The process then continues by combining the scrambled partial code word with the portion of the 1scrambled code word to produce the transmit encoded output data.

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