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Hsiao C Chen

from San Leandro, CA
Age ~48
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Related to:
Tenghui ChenBess P Chen, 46Yingchun Chen, 71Ellen C Sung, 48Leesa R Riches, 53Huichen TengLifu ChengKevin Y Chen, 47Chang Chen Kuo, 55Hsiu Y ChenJudy Chu, 58Deying Jiang, 80
Connected to:
Abre G Chen, 65Adele Chen, 52Adeline K Chen, 39Ai M Chen, 60Ai C Chen, 79Aiping Chen, 63Alen Y Chen, 68Alma Chen, 29Amanda Chen, 44Amanda T Chen, 63

Hsiao Chen Phones & Addresses

  • San Leandro, CA
  • Tracy, CA
  • Berkeley, CA

Resumes

Resumes

Hsiao Chen Photo 1

Company Owner

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Work:
Rtoverseas
Company Owner

Business Records

Name / Title
Company / Classification
Phones & Addresses
Hsiao M. Chen
President
AEC (JB) GROUP CORP
Whol Computers/Peripherals · Commercial Art/Graphic Design Whol Computers/Peripherals
7636 Red Hl Ct, Dublin, CA 94568
16057 Ml Ave, San Lorenzo, CA 94580
(925) 361-8208, (925) 361-8483, (510) 278-0328
Hsiao C. Chen
President
Hot PC to Go Inc
Ret Computers/Software
28996 Hopkins St, Hayward, CA 94545
Hsiao Ling Chen
President
NEW ANGEL MARBLE CORPORATION
390 Swift Ave #10, South San Francisco, CA 94080

Publications

Us Patents

Desensitizing Static Random Access Memory (Sram) To Process Variation

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US Patent:
7746717, Jun 29, 2010
Filed:
Sep 7, 2007
Appl. No.:
11/899825
Inventors:
Tao Peng - Santa Clara CA, US
Hsiao Hui Chen - Sunnyvale CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 7/02
US Classification:
3652101, 36521011, 365193, 365205, 3651852
Abstract:
A static random access memory (SRAM) can include an array of memory cells, wherein each memory cell is coupled to one of a plurality of sense amplifiers through a bitline. The SRAM also can include replica bitline circuitry including a replica bitline coupled to a replica bitline amplifier. The replica bitline amplifier can provide a strobe signal to the plurality of sense amplifiers, wherein the replica bitline amplifier includes a feedback path. An SRAM also may include a write replica circuit generating a signal when data has been written to the write replica circuit. A wordline of the memory array can be turned off responsive to the signal.

Desensitizing Static Random Access Memory (Sram) To Process Variations

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US Patent:
8116119, Feb 14, 2012
Filed:
Apr 12, 2010
Appl. No.:
12/758579
Inventors:
Tao Peng - Santa Clara CA, US
Hsiao Hui Chen - Milpitas CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 11/00
US Classification:
365154, 257903, 365156, 3652101
Abstract:
A static random access memory (SRAM) can include a plurality of columns forming a memory array, wherein each column comprises a plurality of memory cells coupled to bitlines and wordlines, and a write replica circuit generating a signal when data has been written to the write replica circuit. A wordline of the memory array is turned off responsive to the signal. The write replica circuit can include an additional column comprising at least one dual port dummy memory cell, and write detection circuitry coupled to the dual port dummy memory cell detecting when data has been written to the dual port dummy memory cell and responsively generating the signal. The signal generated by the write detection circuitry indicates a successful write operation to the dual port dummy memory cell.

Dual Port Memory With Write Assist

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US Patent:
8295099, Oct 23, 2012
Filed:
May 28, 2010
Appl. No.:
12/790632
Inventors:
Santosh Yachareni - San Jose CA, US
Subodh Kumar - San Jose CA, US
Hsiao Chen - Campbell CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 7/10
G11C 8/00
US Classification:
36518904, 36523005
Abstract:
A data value is read from one port of a dual-port memory cell during a clock cycle. A WRITE assist pulse having a delay from an end-of-read signal is generated. The delay and duration of the WRITE assist pulse are optionally user-selectable. A high voltage (e. g. , Vdd) is coupled to the bitlines (e. g. , BL-A, BLc-A) of the first port during the WRITE assist pulse, and a low voltage value (e. g. , zero) is written to the memory cell through the second port (e. g. , BL-B, BLc-B) during the clock cycle.

Unified Payment Account Establishment And Incorporation In A Main Payment Account

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US Patent:
20200074538, Mar 5, 2020
Filed:
Nov 5, 2019
Appl. No.:
16/675046
Inventors:
- San Jose CA, US
Hsiao Chen - San Jose CA, US
International Classification:
G06Q 40/02
G06Q 20/22
G06Q 20/08
G06Q 20/10
Abstract:
There is provided systems and method for unified payment account establishment and incorporation in a main payment account. A service provider, such as a payment provider, may offer merchants with a development kit that unifies payment methods between various merchants and the service provider so that users are provided with more easily established payment accounts with the merchants. The development kit may include an account establishment interface that may be utilized in a merchant ordering and payment application for a merchant. The interface may provide for establishment of a payment account with the merchant. When initially establishing the payment account, the user may generate a provisional account, which may be synchronized to a payment account the user has with the service provider. When synchronizing the two accounts, the user may transfer information to the merchant, which may be redacted to prevent the merchant from receiving sensitive information.

Unified Payment Account Establishment And Incorporation In A Main Payment Account

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US Patent:
20150339767, Nov 26, 2015
Filed:
Dec 30, 2014
Appl. No.:
14/586899
Inventors:
- San Jose CA, US
Hsiao Chen - San Jose CA, US
International Classification:
G06Q 40/02
G06Q 20/10
Abstract:
There is provided systems and method for unified payment account establishment and incorporation in a main payment account. A service provider, such as a payment provider, may offer merchants with a development kit that unifies payment methods between various merchants and the service provider so that users are provided with more easily established payment accounts with the merchants. The development kit may include an account establishment interface that may be utilized in a merchant ordering and payment application for a merchant. The interface may provide for establishment of a payment account with the merchant. When initially establishing the payment account, the user may generate a provisional account, which may be synchronized to a payment account the user has with the service provider. When synchronizing the two accounts, the user may transfer information to the merchant, which may be redacted to prevent the merchant from receiving sensitive information.
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Hsiao C Chen from San Leandro, CA, age ~48 Get Report