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Binh Vo Phones & Addresses

  • Saratoga, CA
  • 48 Rain Walk, Milpitas, CA 95035 (408) 946-7522
  • San Jose, CA
  • Mountain View, CA
  • Santa Clara, CA

Professional Records

Medicine Doctors

Binh Vo Photo 1

Binh Viet Vo

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Specialties:
Ophthalmology
Education:
Uniformed Services University (2001)

License Records

Binh C Vo

License #:
E040795 - Expired
Category:
Emergency medical services
Issued Date:
Mar 16, 2010
Expiration Date:
Mar 31, 2012
Type:
Los Angeles County EMS Agency

Resumes

Resumes

Binh Vo Photo 2

Software Engineer

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Location:
19271 Valle Vista Dr, Saratoga, CA 95070
Industry:
Computer Software
Work:
Google 2014 - 2016
Software Engineer

Google 2006 - 2006
Intern

Microsoft 2004 - 2004
Research Intern

Precache 2001 - 2002
Part-Time Contractor

At&T 1999 - 2000
Research Intern
Education:
Columbia University In the City of New York 2008 - 2014
Doctorates, Doctor of Philosophy, Computer Science, Philosophy
Massachusetts Institute of Technology 2000 - 2006
Masters, Computer Science
Skills:
Java
Software Development
C#
Python
Software Engineering
Mapreduce
Xml
Distributed Systems
Interests:
Cooking
Medicine
Electronics
Exercise
Investing
Home Improvement
Reading
Crafts
Fitness
Gourmet Cooking
Food
Home Decoration
Health
Languages:
English
Vietnamese
Binh Vo Photo 3

Senior Software Engineer

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Location:
Berkeley, CA
Industry:
Telecommunications
Work:
Shoretel
Senior Software Engineer
Skills:
Sip
Unified Communications
Voip
Ip
Cloud Computing
Linux
Mpls
Telephony
Ethernet
Tcp/Ip
Sip Trunking
Wireless
Lan Wan
Binh Vo Photo 4

Software Manager

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Location:
San Francisco, CA
Industry:
Computer Software
Work:
Check Point Software Technologies, Ltd.
Software Manager

Nokia 1998 - Apr 2009
Senior Software Manager

Lockheed Martin Jun 1997 - Jul 1998
Senior Software Engineer

Visa Dec 1995 - May 1997
Senior Sofware Engineer

Siemens Healthcare Jun 1995 - Dec 1995
Senior Software Engineer
Education:
California State University, Fullerton
Master of Science, Masters, Computer Science
De Anza College
Associates, Accounting
Uc Irvine
Bachelors, Computer Science
Skills:
Security
Software Development
Checkpoint
Tcp/Ip
Network Security
System Architecture
Operating Systems
Integration
Linux
Unix
Web Applications
Cloud Computing
Software Engineering
Firewalls
Enterprise Software
Perl
Solaris
Binh Vo Photo 5

Binh Vo

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Binh Vo Photo 6

Binh Vo

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Binh Vo Photo 7

Binh Vo

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Binh Vo Photo 8

Binh Vo

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Binh Vo Photo 9

Binh Vo

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Binh Vo
President
LUXUREST
26250 Corporate Ave SUITE G, Hayward, CA 94545
Binh Vo
President
MODERN FURNITURE
PO Box 32998, San Jose, CA 95152

Publications

Us Patents

Techniques For Automatically Generating Tests For Programmable Circuits

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US Patent:
7024327, Apr 4, 2006
Filed:
Dec 18, 2002
Appl. No.:
10/323506
Inventors:
Jayabrata Ghosh Dastidar - Santa Clara CA, US
Adam Wright - Santa Clara CA, US
Hung Hing Anthony Pang - San Jose CA, US
Binh Vo - San Jose CA, US
Ajay Nagarandal - Sunnyvale CA, US
Paul J. Tracy - Sunnyvale CA, US
Michael Harms - Pleasanton CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G01R 31/00
G01R 31/14
US Classification:
702117
Abstract:
Programmable circuits have a programmable interconnect structure that connects programmable circuit elements. Tests patterns can be automatically generated for the programmable circuit elements and interconnections on a programmable circuit. A connectivity graph represents programmable interconnections and functions as nodes. Tests routes are generated that connect the nodes in the connectivity graph between control points and observation points on the programmable circuit. The routes are grouped into configuration patterns that can be tested in one test cycle. Test vectors are then applied to the routes to determine if the interconnects and circuit functions are operable. Systems and methods of the present invention automatically create test patterns for a programmable circuit to reduce engineer time. The present invention also reduces test time and resources by increasing the number of interconnections and circuit elements tested in each configuration pattern.

Method And System For Semiconductor Device Characterization Pattern Generation And Analysis

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US Patent:
7571412, Aug 4, 2009
Filed:
Mar 15, 2006
Appl. No.:
11/377714
Inventors:
Hung Hing Anthony Pang - San Jose CA, US
Binh Vo - San Jose CA, US
Souvik Ghosh - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 12, 716 13, 716 14, 716 15, 716 16, 714724, 714725, 703 14, 703 19
Abstract:
A method for generating automatic design characterization patterns for integrated circuits (IC) is provided. The method includes selecting a routing scheme from a file containing the device description of the routings of the IC. The routing scheme may be of a phase locked loop, clock tree, delay element, or input output block in one embodiment. Resource types for the routing scheme are identified and a path is defined, within constraints, between the resources. Once a path is defined, alternate paths are defined by retracing the path within constraints from an end of the path to the beginning of the path. An alternative path is then built and the alternative path shares a portion of the path previously defined. A computing system providing the functionality of the method is also provided.

Functional Failure Analysis Techniques For Programmable Integrated Circuits

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US Patent:
7685485, Mar 23, 2010
Filed:
Oct 30, 2003
Appl. No.:
10/698739
Inventors:
Binh Vo - San Jose CA, US
Wan-Pin Hung - Saratoga CA, US
David Huang - Fremont CA, US
Peter Boyle - Mountain View CA, US
Qi Richard Chen - Sunnyvale CA, US
Kaiyu Ren - San Jose CA, US
Adam J. Wright - San Jose CA, US
John DiCosola - Pleasanton CA, US
Laiq Chughtai - Fremont CA, US
Seng Yew Lim - Penang, MY
Assignee:
Altera Corporation - San Jose CA
International Classification:
G01R 31/28
US Classification:
714725, 714 25
Abstract:
Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.

Method And System For Tokenized Stream Compression

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US Patent:
8010510, Aug 30, 2011
Filed:
Jul 2, 2008
Appl. No.:
12/167116
Inventors:
Binh Vo - Mountain View CA, US
Gurmeet Singii Manku - Mountain View CA, US
Assignee:
Google Inc. - Mountain View CA
International Classification:
G06F 7/00
G06F 17/30
US Classification:
707693
Abstract:
A tokenized stream including n tokens, each token including two or more portions, is received and a first sort order based on a sort of a set of the first portions of the n tokens is determined. The first sort order is applied to reorder a set of the second portions of the n tokens. The above steps are repeated to determine a sort order based on a set of portions of the n tokens and to apply the sort order to another set of portions of the n tokens column until a cset of portions been reordered by a (c−1)sort order. The variable c is a desired number of sets to be sorted. The variables c and n are whole numbers and the n tokens are dispersed during reordering.

Automatic Test Pattern Generation System For Programmable Logic Devices

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US Patent:
8516322, Aug 20, 2013
Filed:
Sep 28, 2009
Appl. No.:
12/568136
Inventors:
Jayabrata Ghosh Dastidar - Santa Clara CA, US
Alok Shreekant Doshi - Sunnyvale CA, US
Binh Vo - Los Gatos CA, US
Kalyana Ravindra Kantipudi - Sunnyvale CA, US
Sergey Timokhin - Palo Alto CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G01R 31/3183
G01R 31/40
US Classification:
714738, 714725
Abstract:
A programmable integrated circuit may contain multiple logic blocks. Computing equipment may be used to run automated tools that process a design for the programmable integrated circuit to perform corresponding circuit tests. A translation tool may translate a transistor-level description of circuitry on the programmable integrated circuit into a gate-level description. A block-level test configuration data generation tool may generate block-level test configuration data files. The test configuration data files may be used as constraints for an automatic test pattern generation tool that produces block-level test vectors. A full-chip propagation tool may use the block-level test vectors, block-level test configuration data files, and full-chip constraints to produce corresponding full-chip test configuration data and full-chip test vectors for testing the integrated circuit. A translation tool may convert the configuration data and test vectors into a tester file.

Electrophoresis Method And Apparatus For Separating Bio-Organic Molecules

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US Patent:
59936282, Nov 30, 1999
Filed:
Apr 17, 1998
Appl. No.:
9/062381
Inventors:
Barton G. Selby - San Carlos CA
Johan Goudberg - San Jose CA
Binh Vo - San Jose CA
David Clark - Hayward CA
Assignee:
The Perkin-Elmer Corporation - Foster City CA
International Classification:
G01N 2726
G01N 27447
US Classification:
204470
Abstract:
The present invention relates to the electrophoretic separation of bio-organic molecules using a slab gel electrophoresis apparatus having a pair of spaced, confronting plates defining a multi-lane separation zone adapted to hold a separation medium and an upper loading zone. In one aspect of the invention, at least one of the plates is shaped to provide an expanded loading zone. The plate-to-plate distance within the expanded loading zone is greater than the plate-to-plate width within the separation zone. In another aspect of the invention, a comb is provided with each tooth having a gradual taper beginning at a support member and extending along most of the tooth's longitudinal axis, and a sharp taper beginning immediately beyond the gradual taper and extending to the end of the tooth. In a related aspect of the invention, a method is provided wherein a comb is inserted into the loading zone so that the teeth penetrate an upper portion of the separation medium, thereby forming a series of fluid-tight, elongate sample-loading apertures of substantially rectangular cross-section having a plate-to-plate width greater than that of the inter-plate distance in the separation zone.

Electrophoresis Method And Apparatus For Separating Bio-Organic Molecules

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US Patent:
61714631, Jan 9, 2001
Filed:
Apr 28, 1999
Appl. No.:
9/301080
Inventors:
Barton G. Selby - San Carlos CA
Johan Goudberg - San Jose CA
Binh Vo - San Jose CA
David Clark - Hayward CA
Thomas Schefer - Reinheim, DE
Munechika Sakabe - Hasuda, JP
Assignee:
The Perkin-Elmer Corporation - Foster City CA
International Classification:
G01N 2726
G01N 27447
US Classification:
204456
Abstract:
The present invention relates to the electrophoretic separation of bio-organic molecules using a slab gel electrophoresis apparatus having a pair of spaced, confronting plates defining a multi-lane separation zone adapted to hold a separation medium and an upper loading zone. In one aspect of the invention, at least one of the plates is shaped to provide an expanded loading zone. The plate-to-plate distance within the expanded loading zone is greater than the plate-to-plate width within the separation zone. In another aspect of the invention, a comb is provided with each tooth having a gradual taper beginning at a support member and extending along most of the tooth's longitudinal axis, and a sharp taper beginning immediately beyond the gradual taper and extending to the end of the tooth. In a related aspect of the invention, a method is provided wherein a comb is inserted into the loading zone so that the teeth penetrate an upper portion of the separation medium, thereby forming a series of fluid-tight, elongate sample-loading apertures of substantially rectangular cross-section having a plate-to-plate width greater than that of the inter-plate distance in the separation zone. Methods of separating biomolecule analytes for optimized resolution and increased base reads are also disclosed.
Binh Hung Vo from Saratoga, CA, age ~60 Get Report